PowerPC Architecture Compliance
7-4
MPC823 USER’S MANUAL
MOTOROLA
PPC
ARCHITECTURE
7
COMPLIANCE
7.2 POWERPC VIRTUAL ENVIRONMENT ARCHITECTURE (BOOK II)
7.2.1 Storage Model
The MPC823 caches are structured as follows:
Physically addressed split 2K instruction cache and 1K data cache
Two-way set associative managed with LRU replacement algorithm
16-byte (4 words) line size with one valid bit per line
7.2.1.1 MEMORY COHERENCE. Hardware memory coherence is not supported in the
MPC823 hardware, but can be performed in the software or by defining storage as cache
inhibited. In addition, the MPC823 does not provide any data storage attributes to an
external system.
7.2.1.2 ATOMIC UPDATE PRIMITIVES. Both the lwarx and stwcx instructions are
implemented according to the PowerPC architecture requirements. When the storage
accessed by the lwarx and stwcx instructions is in the cache-allowed mode, it is assumed
that the system works with the single master in this storage region. Therefore, if a data
cache miss occurs, the access on the internal and external buses does not have a
reservation attribute.
The MPC823 does not cause the system data storage error handler to be invoked if the
storage accessed by the lwarx and stwcx instructions is in the writethrough required mode.
Also, the MPC823 does not provide support for snooping an external bus activity outside the
chip. The provision is made to cancel the reservation inside the MPC823 by using the CR_B
and KR_B input pins. Data cache has a snoop logic to monitor the internal bus for
communication processor module accesses of the address associated with the last lwarx
instruction.
7.2.2 The Effect Of Operand Placement on Performance
The load/store unit hardware supports all of the PowerPC load/store instructions. An optimal
performance can be obtained for naturally aligned operands. These accesses result in
optimal performance for a maximum size of four bytes and good performance for double
precision floating-point operands. Unaligned operands are supported in the hardware and
are broken into a series of aligned transfers. The effect of operand placement on
performance is as stated in the
PowerPC Virtual Environment Architecture (Book II), except
for the case of 8-byte operands. Because the MPC823 uses a 32-bit wide data bus, the
performance is good rather than optimal
Instructions for a description of fixed-point unaligned instruction execution and timing and