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Communication Processor Module
16-144
MPC823 USER’S MANUAL
MOTOROLA
SERIAL
I/F
COMMUNICATION
16
PROCESSOR
MODULE
16.7.6.2.1 IDL Interface Programming Example. Using the example in Section as a
base model, the initialization sequence is as follows:
1. Assuming SMC1 is connected to the B1 channel, SMC2 is connected to the B2
channel, and SCC2 is connected to the D channel, program the serial interface RAM.
Write all entries that are not used with 0x0001, set the LST bit, and disable the routing
function.
2. SIMODE = 0x80008145. Only TDMa is used. The two SMCs are connected to the
time-slot assigner.
3. SICR = 0x0000c000. SCC2 is connected to the time-slot assigner. SCC2 supports the
grant mechanism since it is on the D channel.
4. PAODR bit 9 = 1. Configure L1TXDa to be an open-drain output.
5. PAPAR bits 9, 8, and 7 = 1. Configure L1TXDa, L1RXDa, and L1RCLKa.
6. PADIR bits 9 and 8 = 1. PADIR bit 7 = 0. Configure L1TXDa, L1RXDa, and L1RCLKa.
7. PCPAR bits 12, 5, and 11 = 1. Configure L1RQa, L1TSYNCa, and L1RSYNCa.
8. PCDIR bit 12 = 0. L1RQa is an input. L1TSYNCa performs the L1GRa function and is
therefore an output, but it does not need to be configured with PCDIR bit 5 = 0.
L1RSYNCa is an input, but it does not need to be configured with a PCDIR bit.
9. SIGMR = 0x04. Enable TDMa (one static TDM).
10. SICMR is not used.
11. SISTR and SIRP do not need to be read, but can be used for debugging information
once the channels are enabled.
12. Enable SCC2 to HDLC operation (to handle the LAPD protocol of the D channel). Set
SCC2 and SMC1 to transparent operation.
ENTRY
NUMBER
RAM WORD
SWTR
SSEL
CSEL
CNT
BYT
LST
DESCRIPTION
1
0
0000
101
0000
1
0
8 Bits SMC2 (B1)
2
0
0000
010
0000
0
1 Bit SCC2 (D)
3
0
0000
000
0000
0
1 Bit No Support
4
0
0000
110
0000
1
0
8 Bits SMC2 (B2)
5
0
0000
010
0000
0
1
1 Bit SCC2
Note: Since IDL requires the same routing for both receive and transmit, an exact
duplicate of the above entries should be written to both the receive and transmit
sections of the serial interface RAM beginning at serial interface RAM addresses
0 and 128, respectively.