Communication Processor Module
MOTOROLA
MPC823 USER’S MANUAL
16-413
SMC
COMMUNICATION
16
PROCESSOR
MODULE
16.11.7.13 SMC TRANSPARENT MASK REGISTER. When the SMC is in transparent
mode, the 8-bit read/write SMC mask register is referred to as the SMC transparent mask
(SMCM–Transparent) register. It has the same bit format as the SMCE–Transparent
register. If a bit in this register is a 1, the corresponding interrupt in theSMCE–Transparent
register is enabled. If the bit is zero, the corresponding interrupt is masked.
16.11.7.14 SMC TRANSPARENT NMSI PROGRAMMING EXAMPLE. The following is an
example initialization sequence for SMC1 transparent channel over its own set of pins. The
transmit and receive clocks are provided from the CLK3 pin and the SMSYN1 pin is used to
obtain synchronization.
1. Configure the port B pins to enable the SMTXD1, SMRXD1, and SMSYN1. Write
PBPAR bits 25, 24, and 23 with ones and then PBDIR and PBODR bits 25, 24, and 23
with zeros.
2. Configure the port A pins to enable CLK3. Write PAPAR bit 5 with a one and PADIR
bit 5 with a zero. The other functions of this pin are the timers or the time-slot assigner.
These alternate functions cannot be used on this pin.
3. Connect the CLK3 clock to SMC1 using the serial interface. Write the SMC1 bit in the
SIMODE register with a 0 and the SMC1CS field in the SIMODE register with 110.
4. Write RBASE and TBASE in the SMC parameter RAM to point to the RX buffer
descriptor and TX buffer descriptor in the dual-port RAM. Assuming one RX buffer
descriptor at the beginning of the dual-port RAM and one TX buffer descriptor following
that RX buffer descriptor, write RBASE with 0x2000 and TBASE with 0x2008.
5. Program the CPCR to execute the INIT RX AND TX PARAMS command. Write
0x0091 to the CPCR.
6. Write 0x0001 to the SDCR to initialize the SDMA configuration register.
7. Write 0x18 to RFCR and TFCR for normal operation.
8. Write MRBLR with the maximum number of bytes per receive buffer. Assume 16
bytes, so MRBLR = 0x0010.
9. Initialize the RX buffer descriptor and assume the RX data buffer is at 0x00001000 in
main memory. Write 0xB000 to RX_BD_Status, 0x0000 to RX_BD_Length (optional),
and 0x00001000 to RX_BD_Pointer.
SMCM–TRANSPARENT
BIT
0
1
2
3
4
5
6
7
FIELD
RESERVED
TXE
RES
BSY
TX
RX
RESET
0
00000
R/W
R/W
ADDR
(IMMR & 0xFFFF0000) + 0xA8A (SMC1), 0xA9A (SMC2)