
Communication Processor Module
16-384
MPC823 USER’S MANUAL
MOTOROLA
SMC
COMMUNICATION
16
PROCESSOR
MODULE
By appropriately setting the I bit in each buffer descriptor, interrupts can be generated after
the transmission of each buffer, a specific buffer, or each block. The SMC UART controller
then proceeds to the next buffer descriptor in the table. If the CM bit is set in the TX buffer
descriptor, the R bit is not cleared, allowing the associated data buffer to be automatically
retransmitted next time the communication processor module accesses this data buffer. For
instance, if a single TX buffer descriptor is initialized with the CM and W bits set, the data
buffer is continuously transmitted until you clear the R bit of the buffer descriptor.
16.11.6.3 SMC UART CHANNEL RECEPTION PROCESS. When the core enables the
SMC receiver in UART mode, it enters hunt mode and waits for the first character to arrive.
Once the first character arrives, the communication processor module checks the first RX
buffer descriptor to see if it is empty and then starts storing characters in the associated data
buffer.
When the data buffer is filled or the MAX_IDL timer expires if it is enabled, the SMC UART
controller clears the E bit in the buffer descriptor and generates an interrupt if the I bit in the
buffer descriptor is set. If the incoming data exceeds the length of the data buffer, the SMC
UART controller fetches the next buffer descriptor in the table and, if it is empty, continues
transferring data to this buffer descriptor associated data buffer. If the CM bit is set in the RX
buffer descriptor, the E bit is not cleared, which allows the associated data buffer to be
automatically overwritten next time the communication processor module accesses this
data buffer.
16.11.6.4 SMC UART PARAMETER RAM MEMORY MAP. When configured to operate
in UART mode, the SMC UART controller overlays the structure used in
Table 16-36 withTable 16-37. SMC UART Parameter RAM Memory Map
ADDRESS
NAME
WIDTH
DESCRIPTION
SMC Base + 28
MAX_IDL
Half-word
Maximum Idle Characters
SMC Base + 2A
IDLC
Half-word
Temporary Idle Counter
SMC Base + 2C
BRKLN
Half-word
Last Received Break Length
SMC Base + 2E
BRKEC
Half-word
Receive Break Condition Counter
SMC Base +30
BRKCR
Half-word
Break Count Register (Transmit)
SMC Base +32
R_MASK
Half-word
Temporary Bit Mask
NOTE:
You are only responsible for initializing the items in bold.
SMC Base = (IMMR & 0xFFFF0000) + 0x3E80 (SMC1) and 0x3F80 (SMC2).