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Memory Controller
MOTOROLA
MPC823 USER’S MANUAL
15-43
MEMORY
CONTROLLER
15
MEMORY
CONTROLLER
15
15.5.1.1 INTERNAL/EXTERNAL MEMORY ACCESS REQUESTS. When any of the
internal masters request a new access to external memory, the address and type of the
transfer are compared to each one of the valid banks defined in the base register. The value
of the MS field in the base register selects the UPM that will handle the memory access. You
must ensure that the appropriate UPM entries are created prior to your request.
The external memory access requests consist of read single beat, read burst, write single
beat, and write burst. A single beat cycle is generated by the master to a cache-inhibited
memory bank. A typical burst cycle is generated to the memory that allows multiple
accesses. It only occurs when your memory is burstable. A single beat cycle starts out with
one transfer start and ends with one transfer acknowledge. For a 32-bit access, the burst
cycle starts out with one transfer start but ends with four transfer acknowledges. For a 16-bit
bus, there are eight transfer acknowledges. For an 8-bit bus, there are 16 transfer
acknowledges.
15.5.1.2 MEMORY PERIODIC TIMER REQUESTS. Each UPM contains a periodic timer
that can be programmed to generate periodic service requests that will be indexed into the
RAM array.
Figure 15-22 illustrates the hardware associated with memory periodic timer
request generation. In general, the periodic timer is used for refresh cycle operation.
15.5.1.3 SOFTWARE REQUESTS. The software can initiate a request to the
user-programmable machine by issuing one of three commands—read, write, or execute a
RAM word— to the memory command register. Every memory device has its own signal
handshaking protocol to put it into self-refresh mode or any special protocol mode. In the
user-programmable machine there are unused areas that enable you to write a special RAM
word for this protocol. Any unused area in the UPM RAM can be used to store these RAM
words. Typically, software requests are used to put the memory in self-refresh mode. You
can use this method to maintain memory integrity before going into low-power or lower
power modes. A new command must be issued to exit self-refresh mode or any special
protocol mode after returning to normal operation.
Figure 15-22. Memory Periodic Timer Request Block Diagram
UPMA PERIODIC
UPMB PERIODIC
PERIODIC
MEMORY
SYSTEM
BRG PRESCALER
TIMER REQUEST
CLOCK
PERIODIC
TIMER
PRESCALER
(IN THE MPTPR)
TIMER A
(PTA)
PERIODIC
TIMER B
(PTB)
(IN THE SCCR)