Communication Processor Module
16-320
MPC823 USER’S MANUAL
MOTOROLA
SCC2
COMMUNICATION
16
PROCESSOR
MODULE
C_PRES—For 32-bit CRC-CCITT, C_PRES should be initialized with 0xFFFFFFFF.
C_MASK—For 32-bit CRC-CCITT, C_MASK should be initialized with 0xDEBB20E3.
CRCEC, ALEC, and DISFC—These 32-bit (modulo 2
32) counters are maintained by the
communication processor module and you can initialize them while the channel is
disabled. CRCEC is incremented for each received frame with a CRC error, except it
does not include frames not addressed to you, frames received in the out-of-buffers
condition, frames with overrun errors, or frames with alignment errors. ALEC is
incremented for frames received with dribbling bits, but does not include frames not
addressed to you, frames received in the out-of-buffers condition, or frames with
overrun errors. DISFC is incremented for frames discarded because of the
out-of-buffers condition or an overrun error. The CRC does not have to be correct for
this counter to be incremented.
PADS—You must write the pattern of the pad characters that should be sent when short
frame padding is implemented into this 16-bit register. The byte pattern written to the
register may be of any value, but both the high and low bytes should be the same.
RET_LIM—You must write the number of retries that should be made to transmit a
frame into this 16-bit register. This value is typically 0xF. If the frame is not transmitted
after this limit is reached, an interrupt can be generated.
RET_CNT is a temporary down-counter used to count the number of retries made.
MFLR—The SCC2 Ethernet controller checks the length of an incoming Ethernet frame
against the user-defined value given in this 16-bit register. Typically this register is set
to 0x5EE. If this limit is exceeded, the remainder of the incoming frame is discarded and
the LG bit is set in the last RX buffer descriptor belonging to that frame. The SCC2
Ethernet controller reports the frame status and length in the last RX buffer descriptor.
MFLR is defined as all the in-frame bytes between the start frame delimiter and the end
of the frame.
MINFLR—The SCC2 Ethernet controller checks the length of an incoming Ethernet
frame against the user-defined value given in this 16-bit register that is typically set to
0x40. If the received frame length is less than the register value, then this frame is
discarded unless the RSH bit in the PSMR–SCC2 Ethernet is set. If RSH is set, then
the SH bit is set in the last RX buffer descriptor belonging to that frame. For transmit
operation when the frame is too short, the SCC2 Ethernet controller adds PADs to the
transmitted frame, depending on how the PAD bit is set in the TX buffer descriptor and
the PAD value in the parameter RAM. Pad characters are added to make the transmit
frame MINFLR bytes in length.
MAXD1—This parameter gives you the option to stop system bus writes from occurring
after a frame has exceeded a certain size. However, the value of this register is valid
only if an address match is found. The SCC2 Ethernet controller checks the length of
an incoming Ethernet frame against the user-defined value given in this 16-bit register
that is usually set to 0x5F0. If this limit is exceeded, the remainder of the incoming frame
is discarded. The SCC2 Ethernet controller waits to the end of the frame or until MFLR
bytes have been received and reports the frame status and the frame length in the last
RX buffer descriptor.