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The PowerPC Core
6-14
MPC823 USER’S MANUAL
MOTOROLA
CORE
6
6.3.8 Interrupt Ordering
There are two main types of interrupts:
Instruction-related interrupts
Asynchronous interrupts
Instruction-related exceptions (interrupt causes) are detected while the instruction is in
various stages of being processed by the core. Exceptions found early in instruction
processing preclude detection of further exceptions. This earlier interrupt will eventually be
taken. If more than one instruction in the pipeline causes an exception, only the first
exception is taken and causes an interrupt. The remaining instruction-induced exceptions
are ignored. The following table lists the instruction-related interrupts in the order of
detection within the instruction processing.
Table 6-5. Instruction-Related Interrupt Detection Order
NUMBER
INTERRUPT TYPE
CAUSE
1
Trace
Trace Bit Asserted1
2
Implementation Dependent Instruction TLB
Miss
Instruction Memory Management Unit TLB Miss
3
Implementation Dependent Instruction TLB
Error
Instruction Memory Management Unit
Protection / Translation Error
4
Machine Check Interrupt
Fetch Error
5
Debug I- Breakpoint
Match Detection
6
Implementation Dependent Software Emulation
Interrupt
Attempt to Invoke Unimplemented Feature
1
Floating-Point Unavailable
Attempt to is Made to Execute Floating-Point
Instruction and MSRFP =0
72
Privileged Instruction
Attempt to Execute Privileged Instruction in
Problem Mode
Alignment Interrupt
Load/Store Checking
System Call Interrupt
SC Instruction
Trap
Trap Instruction
8
Implementation Dependent Data TLB Miss
Data Memory Management Unit TLB Miss
9
Implementation Dependent Data TLB Error
Data Memory Management Unit TLB Protection/
Translation Error
10
Machine Check Interrupt
Load or Store Access Error
11
Debug L- Breakpoint
Match Detection
NOTES:
1.
The trace mechanism is implemented by letting one instruction go as if no trace is enabled and
trapping the second instruction. This, of course, refers to this second instruction.
2.
Exclusive for any one instruction.