PowerPC Architecture Compliance
MOTOROLA
MPC823 USER’S MANUAL
7-5
PPC
ARCHITECTURE
7
COMPLIANCE
7.2.3 The Storage Control Instructions
The MPC823 interprets the cache control instructions (icbi, isync, dcbt, dcbi, dcbf, dcbz,
dcbst, eieio, and dcbtst) as if they pertain only to the MPC823 cache. These instructions
do not broadcast. Any bus activity caused by these instructions is what happens when an
operation is performed on the MPC823 cache.
Instruction Cache Block Invalidate (icbi)—The effective address is translated by the
memory management unit and the associative block in the instruction cache is
invalidated if hit.
Instruction Synchronize (isync)—The isync instruction waits for all previous
instructions to complete and then discards any prefetched instructions, thus causing
subsequent instructions to be fetched or refetched from memory and executed.
Data Cache Block Touch (dcbt)—The block associated with this instruction is checked
for hit in the cache. If it is a miss, the instruction is treated as a regular miss, except that
the bus error does not cause an interrupt. If no error occurs, the line is written into the
cache.
Data Cache Block Touch for Store (dcbtst)—The block associated with this instruction
is checked for a hit in the cache. If it is a miss, the instruction is treated as a regular
miss, except that bus error does not cause an interrupt. If no error occurs, the signal is
written into the cache.
Data Cache Block Set to Zero (dcbz)—This instruction is executed according to how it
is defined in the
PowerPC Virtual Environment Architecture Book II.
Data Cache Block Store (dcbst)—This instruction is executed according to how it is
defined in the
PowerPC Virtual Environment Architecture Book II.
Data Cache Block Invalidate (dcbi)—The effective address is translated by the memory
management unit and the associative block in the data cache is invalidated if hit.
Data Cache Block Flush (dcbf)—This instruction is executed according to how it is
defined in the
PowerPC Virtual Environment Architecture Book II.
Enforce In-Order Execution of I/O (eieio)—When executing an eieio instruction, the
load/store unit waits until all previous accesses have terminated before issuing cycles
associated with load/store instructions after the eieio instruction.
7.2.4 Timebase