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Communication Processor Module
MOTOROLA
MPC823 USER’S MANUAL
16-489
CPIC
COMMUNICATION
16
PROCESSOR
MODULE
Within the CPM interrupt level, the sources are assigned a priority structure. On the
MPC823, you have some flexibility with the relative priority of the interrupt sources.
Once an unmasked interrupt source is pending in the CIPR, the CPM interrupt controller
sends an interrupt request to the U-Bus at level 0, 1, 2, 3, 4, 5, 6, or 7. The CPM interrupt
controller then waits for the interrupt to be recognized. After the interrupt request is honored
by the core, the core acknowledges the interrupt by setting the IACK bit in the CPM interrupt
vector register. When the IACK bit is set, the CIVR is updated with a 5-bit vector
corresponding to the sub-block with the highest current priority and the IACK is cleared after
one clock cycle.
16.15.1 Features
The following is a list of the CPM interrupt controller’s main features:
Twenty-four Interrupt Sources (12 Internal and 12 External)
Sources Can Be Assigned to a Programmable Interrupt Level
Programmable Priority Between SCC2 and USB
Two Priority Schemes for SCC2 and USB
Programmable Highest Priority Request
Fully Nested Interrupt Environment
Unique Vector Number for Each Interrupt Source
16.15.2 CPM Interrupt Source Priorities
The CPM interrupt controller has 24 interrupt sources that assert a programmable interrupt
request level to the core and the priority between these sources is shown in
Table 16-45.There is some flexibility in the relative ordering of the interrupts in the table, but, in general,
the relative priorities are fixed in the descending order shown. An interrupt from the parallel
I/O signal PC15 has the highest priority and an interrupt from the parallel I/O signal PC4 has
the lowest. A single interrupt priority number is associated with each table entry.
Notice the lack of SDMA interrupt sources. SDMA-related interrupts are reported through
each individual USB, SCC2, SMC, SPI, or I2C channel. The only true SDMA interrupt source
is the SDMA channel bus error entry that is reported when a bus error occurs during an
SDMA access. There are two ways to add flexibility to the table of CPM interrupt priorities
(the USB/SCC2 relative priority option or the highest priority option).