Endian Modes
MOTOROLA
MPC823 USER’S MANUAL
14-5
ENDIAN
MODES
14
14.2 BIG-ENDIAN SYSTEM FEATURES
The following is a list of the big-endian system’s main features:
Caches, U-Bus, E-Bus, System Memory, and I/O Organization Format is Big-Endian
Same Byte Order Between the Media and System Memory
Communication Processor Module Writes and Reads Big-Endian U-Bus Data
PCI Bridge Operates in Big-Endian Mode as Needed
14.3 POWERPC LITTLE-ENDIAN SYSTEM FEATURES
The following is a list of the PowerPC little-endian system’s main features:
Caches, U-Bus, E-Bus, System Memory, and E-Bus Attached I/O Organization Format
is Big-Endian
PCI Bus Format is Little-Endian
Data Access Constraints That Follow the PowerPC Little-Endian Rules
Address Munging in the Core and Communication Processor Module Follows the
The PCI Bridge Operates in Little-Endian Mode as Needed. Swap and Address
Demunging is Performed by the PCI Bridge on the PCI I/O to the System Memory Path.
The Stream Hit Mechanisms of the Instruction and Data Caches Operate Less
Efficiently When Address Munging is Performed on Cache Accesses. Some
Performance Degradation is Expected When Working in this Mode.
14.4 SETTING THE ENDIAN MODE OF OPERATION
The mode should be set early in the reset routine and remain unchanged for the duration of
system operation. The MPC823 core is in big-endian mode after reset. To switch between
the different endian modes of operation, the core must run in serialized mode and the
caches should be disabled. It is not recommended that you switch back and forth between
modes. To transfer the system to the PowerPC little-endian mode, the MSRLE and MSRILE
bits should be changed with the mtmsr instruction that resides on the odd word boundary
(A[29] = 1). The instruction that is executed next will be fetched from this address plus 8. If
the instruction resides on an even word boundary (A[29] = 0), then this instruction will be
executed twice because of address munging.
The instruction used to transfer the system back to big-endian mode must reside on an even
word boundary (A[29] = 0). The next instruction will be fetched from this address plus 12. A
transfer to little-endian mode should be made with the mtspr instruction that resides on the
even word boundary (A[29] = 0). Further instructions should reside in the little-endian format
of the external system memory and in the big-endian format of the internal memory. The BO
field of the function code registers (FCRs) in the communication processor module should
be set to the required endian format for the buffer descriptor.