Development Capabilities and Interface
20-32
MPC823 USER’S MANUAL
MOTOROLA
DEVELOPMENT
20
CAPABILITIES
&
INTERFACE
The first clock mode is called asynchronous clocked since the input clock DSCK is
asynchronous with respect to CLKOUT. To be sure that data on DSDI is sampled correctly,
transitions on DSDI must meet all setup and hold times in respect to the rising edge of
DSCK. This clock mode allows communications with the port from a development tool that
does not have access to the CLKOUT signal or has either a delayed or skewed CLKOUT
clocked timing.
The second clock mode is called synchronous self-clocked and does not require an input
clock. Instead, the port is clocked by the system clock. The DSDI input is required to meet
setup and hold time requirements, with respect to the rising edge of CLKOUT. The data rate
for this mode is always the same as the system clock. The timing diagram in
Figure 20-10illustrates serial communication synchronous self-clocked timing. The selection of clocked
or self-clocked mode is made at reset. The state of the DSDI input is latched eight clocks
after SRESET is negated. If it is latched low, asynchronous clocked mode is enabled. If it is
latched high, then synchronous self-clocked mode is enabled. The timing diagram in
Figure 20-11 illustrates the clock mode selection following reset.
Since DSDI is used to select the development port clock scheme, any transitions on DSDI
during clock mode select must be prevented from being recognized as the start of a serial
transmission. The port will not begin scanning for the START bit of a serial transmission until
16 clocks after SRESET is negated. If DSDI is asserted 16 clocks after SRESET negates,
the port waits until DSDI is negated before it starts scanning for the START bit.
20.4.3.7 TRAP ENABLE MODE. When not in debug mode, the development port begins
communicating by setting DSDO (the MSB of the 35-bit development interface port shift
register) low to show that all activity related to the previous transmission is complete and
that a new transmission can begin. The start of a serial transmission from an external
development tool to the development port is signaled by a START bit. A MODE bit in the
transmission defines it as either a trap enable mode or debug mode transmission. If the
MODE bit is set, the transmission will be 10 bits long and only seven data bits will be shifted
into the shift register. These seven bits will be latched into the TECR. A control bit
determines whether the data is latched into the TECR’s trap enable, VSYNC, or breakpoints
bits.
The development interface port shift register is 35 bits wide, but trap enable mode
transmissions only use 10 of the 35 bits—start/ready, mode/status, control/status, and
seven least-significant data bits. The encoding of data shifted into the development interface