參數(shù)資料
型號(hào): HC05V7GRS
英文描述: 68HC05V7 General Release Specification
中文描述: 68HC05V7一般版本規(guī)范
文件頁(yè)數(shù): 93/170頁(yè)
文件大?。?/td> 980K
代理商: HC05V7GRS
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SECTION 13: PULSE WIDTH MODULATOR
MOTOROLA
Page 79
SECTION 13
PULSE WIDTH MODULATOR
The pulse width modulator (PWM) system has one 6-bit channel (PWMA). Preceding the
6-bit (
÷
64) PWM are two programmable prescalers.The PWM frequency is selected by
choosing the desired divide option from the programmable prescalers. Note that the PWM
clock input is
f
osc
, which is twice the bus frequency. The PWM frequency will be f
osc
/
(PSA+PSB+64) where PSA and PSB are the values selected by the A and B prescaler and
64 comes from the 6-bit modulus counter. See Table 13-1 for precise values. E is the
internal bus frequency fixed to half of the external oscillator frequency.
Figure 13-1: PWM Block Diagram
13.1
The PWM is capable of generating signals from 0% to 100% duty cycle. A $00 in the PWM
Data Register yields an “l(fā)ow” output (0%), but a $3F yields a duty of 63/64. To achieve the
100% duty (“high” output), the polarity control bit is set to zero while the data register has
$00 in it.
When not in use, the PWM system can be shut off to save power by clearing the clock rate
select bits PSA0 and PSA1 in PWMCR.
Writes to the PWM data register are buffered and can therefore be performed at any time
without affecting the output signal. When the PWM subsystem is enabled, a write to the
PWM Control Register will become effective immediately.
FUNCTIONAL DESCRIPTION
6-BIT COUNTER
(
÷
64)
PWM DATA
REGISTER
MODULUS &
COMPARATOR
PWM
PIN LOGIC
PWMA
÷
1,
÷
8,
÷
16
f
osc
P
P
PWM CONTROL REGISTER and BUFFER
H
P
PWM DATA
BUFFER
SCLK
÷
1-16
P
P
P
P
RCLK
Integer divide
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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