參數資料
型號： HC05V7GRS
英文描述： 68HC05V7 General Release Specification
中文描述： 68HC05V7一般版本規(guī)范
文件頁數： 83/170頁
文件大?。?/td> 980K
代理商： HC05V7GRS
SECTION 11: 16-BIT TIMER
MOTOROLA
Page 69
SECTION 11
16-BIT TIMER
The timer consists of a 16-bit, free-running counter driven by a fixed divide-by-four
prescaler. This timer can be used for many purposes, including input waveform
measurements while simultaneously generating an output waveform. Pulse widths can
vary from several microseconds to many seconds.
Figure 11-1: 16-Bit Timer Block
Diagram
.
Because the timer has a 16-bit architecture, each specific functional segment (capability)
is represented by two registers. These registers contain the high and low byte of that
functional segment. Access of the high byte inhibits that specific timer function until the low
byte is also accessed.
NOTE:
The I bit in the CCR should be set while manipulating both the high and
low byte register of a specific timer function to ensure that an interrupt
does not occur.
Figure 11-1: 16-Bit Timer Block Diagram
Input
Capture
Register
Clock
Internal Bus
Output
Compare
Register
High
Byte
Low
Byte
$16
$17
∏∏∏
/4
Internal
16-Bit Free
Running
Counter
Counter
Alternate
Register
8-Bit
Buffer
High
Byte
Low
Byte
$1A
$1B
$18
$19
High
Byte
Low
Byte
$14
$15
Output
Compare
Circuit
Overflow
Detect
Circuit
Edge
Detect
Circuit
Timer
Status
Reg.
ICF OCF TOF$13
ICIE
IEDG OLVL
Output
Level
Reg.
RESET
Timer
Control
Reg.
$12
Output
Level
(TCMP)
PB6
Interrupt
Circuit
TOIE
OCIE
Edge
Input
(TCAP)
PB7
D
CLK
C
Q
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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