參數(shù)資料
型號(hào): HC05V7GRS
英文描述: 68HC05V7 General Release Specification
中文描述: 68HC05V7一般版本規(guī)范
文件頁(yè)數(shù): 61/170頁(yè)
文件大小: 980K
代理商: HC05V7GRS
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SECTION 7: POWER SUPPLY AND REGULATION
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Page 47
This bit has no affect unless the regulator option is set. This bit is not affected by reset and
must be initialized by software.
7.3
POWER MODING
A flow diagram depicting all conditions that the MCU could enter is shown in Figure 7-2.
The chip can be operated in one of three distinct power modes. The first mode is "Power
off". In this mode, the chip is not being powered from any source. The V
BATT
pin voltage is
below that required by the regulator circuit to provide an output voltage that is within
regulation limits.
The second mode is "Standby power". In this mode, the V
BATT
voltage is above the
required minimum, but the user has not turned the primary regulator on. The secondary
regulator and the power mode logic are powered up. Standby mode can be exited by either
reducing the V
BATT
voltage or by turning the primary regulator on.
The third mode is "Power up" mode. In this mode, the CPU and peripherals can perform
their normal processing tasks. The only way to exit from this mode is to lose regulator
output power. Losing regulator output power can happen in one of three ways: 1) the V
BATT
voltage can fall below the required minimum level causing V
DD
to fall below minimum, 2)
software can turn the primary regulator off, and 3) some sort of fault on the external V
DD
pin. In any case, the LVR reset will be asserted to protect the system as the V
DD
voltage is
falling.
Transitioning between these states is referred to as power moding.
F
Freescale Semiconductor, Inc.
n
.
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