參數(shù)資料
型號： HC05V7GRS
英文描述： 68HC05V7 General Release Specification
中文描述： 68HC05V7一般版本規(guī)范
文件頁數(shù)： 90/170頁
文件大?。?/td> 980K
代理商： HC05V7GRS
MOTOROLA
Page 76
SECTION 12: CORE TIMER
MC68HC05V7 Specification Rev. 1.0
As seen in Figure 6-1, the internal peripheral clock is divided by four then drives an 8-bit
ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time by
accessing the Core Timer Counter Register (CTCR) at address $09. A timer overflow
function is implemented on the last stage of this counter, giving a possible interrupt rate of
the Internal Peripheral clock(E)/1024. This point is then followed by two more stages, with
the resulting clock (E/2048) driving the Real Time Interrupt circuit (RTI). The RTI circuit
consists of three divider stages with a 1 of 4 selector. The output of the RTI circuit is further
divided by eight to drive the mask optional COP Watchdog Timer circuit. The RTI rate
selector bits, and the RTI and CTOF enable bits and flags are located in the Timer Control
and Status Register at location $08.
12.1
The CTCSR contains the timer interrupt flag, the timer interrupt enable bits, and the real
time interrupt rate select bits. Figure 12-2 shows the value of each bit in the CTCSR when
coming out of reset.
CORE TIMER CTRL & STATUS REGISTER (CTCSR) $08
Figure 12-2: Core Timer Control and Status Register
12.1.1
CTOF is a read-only status bit set when the 8-bit ripple counter rolls over from $FF to $00.
Clearing the CTOF is done by writing a ‘1’ to TOFC. Writing to this bit has no effect. Reset
clears CTOF.
CTOF - Core Timer Over Flow
12.1.2
The Real Time Interrupt circuit consists of a three stage divider and a 1 of 4 selector. The
clock frequency that drives the RTI circuit is E/2**11 (or E/2048) with three additional
divider stages giving a maximum interrupt period of 7.8 milliseconds at a bus rate of 2.1
MHz. RTIF is a clearable, read-only status bit and is set when the output of the chosen (1
of 4 selection) stage goes active. Clearing the RTIF is done by writing a “1” to RTFC.
Writing has no effect on this bit. Reset clears RTIF.
RTIF - Real Time Interrupt Flag
12.1.3
When this bit is set, a CPU interrupt request is generated when the CTOF bit is set. Reset
clears this bit.
TOFE - Timer Over Flow Enable
12.1.4
When this bit is set, a CPU interrupt request is generated when the RTIF bit is set. Reset
clears this bit.
RTIE - Real Time Interrupt Enable
12.1.5
When a “1” is written to this bit, CTOF is cleared. Writing a “0” has no effect on the CTOF
bit. This bit always reads as zero.
TOFC - Timer Over Flow Flag Clear
CTOF
TOFE
RTIE
TOFC
RTFC
RT1
RT0
RTIF
$08
0
0
0
0
0
1
1
0
RESET:
F
For More Information On This Product,
Go to: www.freescale.com
n
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