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參數(shù)資料
| 型號(hào)： | HC05V7GRS |
| 英文描述： | 68HC05V7 General Release Specification |
| 中文描述： | 68HC05V7一般版本規(guī)范 |
| 文件頁數(shù)： | 115/170頁 |
| 文件大?。?/td> | 980K |
| 代理商： | HC05V7GRS |
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SECTION 15: MESSAGE DATA LINK CONTROLLER
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Page 101
Attempts to send a zero byte message body length (value of $00 written to MTCR) will also
prevent the MDLC from transmitting that message.
Writing a value within the valid range to this register will initiate a transmission regardless
of whether any new data has been loaded into the Tx Buffer. Failure to supply new data
before this register is written to will result in the MDLC transmitting whatever data happens
to be in the Tx Buffer at the time of the write.
Do not write to this register while the TXAB bit in the MCR register is set.
This register will be automatically cleared at the end of any transmission, whether it was
successful, unsuccessful or aborted.
15.2.5
MDLC RX STATUS REGISTER (MRSR) $11
This register reports the status of the MDLC receiver, including the Rx Buffer.
All bits may be read in all modes of MCU operation.
Bits 4, 5, 6, and 7 will always read as zeros and can never be written to.
Bits 0, 1, 2, and 3 can be written to in all modes of MCU operation.
15.2.5.1
RC0,1,2,3 - Receive Count
These bits reflect the number of bytes of the message body in the Rx Buffer available to
the CPU. As a message is being received, the data is placed into successive locations of
one of the two Rx Buffers. The Rx Buffer being filled is not visible to the programmer.
A running count of the number of bytes received is kept internally. The maximum count is
11 bytes. The CRC is
not
placed in the Rx Buffer and is not counted in the final indicated
message length.
Once the message has been received error-free, the Rx Buffer is placed into the MCU’s
memory map, the MRSR is updated with the count of the number of data bytes received, a
CPU interrupt request is generated if the Interrupt Enable (IE) bit is set and the Rx Message
Successful (RXMS) bit will be set in the MSR.
When the programmer has finished analyzing the received message, a write to this register
will signal to the MDLC that the programmer no longer needs the contents of the Rx Buffer.
Figure 15-6: MDLC Rx Status Register (MRSR)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
RC1
RC0
RC2
RC3
0
0
0
0
RESET
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
n
.
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