參數(shù)資料
型號(hào)： HC05V7GRS
英文描述： 68HC05V7 General Release Specification
中文描述： 68HC05V7一般版本規(guī)范
文件頁數(shù)： 73/170頁
文件大?。?/td> 980K
代理商： HC05V7GRS
SECTION 8: LOW-POWER MODES
MOTOROLA
Page 59
Figure 8-2: STOP/WAIT Flowcharts
8.1.2
WAIT INSTRUCTION
The WAIT instruction places the MCU in a low-power mode, which consumes more power
than the STOP Mode. In the WAIT Mode the internal processor clock is halted, suspending
all processor and internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the timer or a reset to be generated from the COP
Watchdog Timer. Execution of the WAIT instruction automatically clears the I-bit in the
Condition Code Register. All other registers, memory, and input/output lines remain in their
previous states.
MDLC
Bus
Edge
Y
N
1.
Fetch Reset Vector
or
Service Interrupt
a.
Stack
b.
Set I-Bit
c.
Vector to Interrupt Routine
2.
WAIT
STOP Mask
Option En-
abled
Y
N
External
RESET
Y
N
IRQ
External
Interrupt
Y
N
Stop External Oscillator,
Stop Internal Timer Clock,
and Reset Startup Delay
Restart External Oscillator,
and Stabilization Delay
Stop Internal Processor Clock,
Clear I-Bit in CCR,
End
of Startup
Delay
Y
N
IRQ
External
Interrupt
Y
N
External Oscillator Active,
and Internal
Timer Clock Active
Restart
Internal Processor Clock
Stop Internal Processor Clock,
Clear I-Bit in CCR,
TIMER
Internal
Interrupt
Y
N
External
RESET
Y
N
STOP
MDLC
Bus
Edge
Y
N
Port A
or C Falling
Edge
Y
N
Port A
or C Falling
Edge
Y
N
Reset Chip
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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