參數(shù)資料
型號： HC05V7GRS
英文描述： 68HC05V7 General Release Specification
中文描述： 68HC05V7一般版本規(guī)范
文件頁數(shù)： 103/170頁
文件大?。?/td> 980K
代理商： HC05V7GRS
SECTION 14: SERIAL PERIPHERAL INTERFACE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Page 89
WCOL - Write Collision
The write collision bit is set when an attempt is made to write to the serial
peripheral data register while data transfer is taking place. If CPHA is zero, a
transfer is said to begin when SS goes low and the transfer ends when SS goes
high after eight clock cycles on SCK. When CPHA is one, a transfer is said to
begin the first time SCK becomes active while SS is low and the transfer ends
when the SPIF flag gets set. Clearing the WCOL bit is accomplished by reading
the SPSR (with WCOL set) followed by an access to SPDR.
Bit 5 - Not implemented
This bit always reads zero.
MODF - Mode Fault
The mode fault flag indicates that there may have been a multi-master conflict
for system control and allows a proper exit from system operation to a reset or
default system state. The MODF bit is normally clear, and is set only when the
master device has its SS pin pulled low. Setting the MODF bit affects the internal
serial peripheral interface system in the following ways:
SPI interrupt is generated if SPIE=1.
SPE bit is cleared. This disables the SPI.
MSTR bit is cleared, thus forcing the device into the slave mode.
Clearing the MODF bit is accomplished by reading the SPSR (with MODF set),
followed by a write to the SPCR. Control bits SPE and MSTR may be restored
to their original state by user software after the MODF bit has been cleared. It is
also necessary to restore DDRD after a mode fault.
Bits 3-0 - Not Implemented
These bits always read zero.
14.3.3
Serial Peripheral Data I/O Register (SPDR)
The serial peripheral data I/O register is used to transmit and receive data on the serial bus.
Only a write to this register will initiate transmission/reception of another byte, and this will
only occur in the master device. At the completion of transmitting a byte of data, the SPIF
status bit is set in both the master and slave devices.
When the user reads the serial peripheral data I/O register, a buffer is actually being read.
The first SPIF must be cleared by the time a second transfer of the data from the shift
register to the read buffer is initiated, or an overrun condition will exist. In cases of overrun,
the byte that causes the overrun is lost.
A write to the serial peripheral data I/O register is not buffered and places data directly into
the shift register for transmission.
SPD7
SPD5
SPD4
SPD3
SPD2
PSD1
SPD0
SPD6
$0C
-
-
-
-
-
-
-
-
RESET:
F
Freescale Semiconductor, Inc.
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