參數(shù)資料
型號: HC05V7GRS
英文描述: 68HC05V7 General Release Specification
中文描述: 68HC05V7一般版本規(guī)范
文件頁數(shù): 89/170頁
文件大?。?/td> 980K
代理商: HC05V7GRS
SECTION 12: CORE TIMER
MOTOROLA
Page 75
SECTION 12
CORE TIMER
The Core Timer for this device is a 12-stage multifunctional ripple counter. The features
include Timer Over Flow, Power-On Reset (POR), Real Time Interrupt (RTI), and COP
Watchdog Timer.
Figure 12-1: Core Timer Block Diagram
COP
Clear
Internal Bus
$09 Core Timer Counter Register (CTCR)
5-bit counter
CTOF
RTIF
TOFE
RTIE
RT1
Interrupt Circuit
$08
RTI Select Circuit
Status Register
RT0
Timer Control &
Overflow
Detect
Circuit
COP Watchdog
Timer (
÷
8)
2
3
To Reset
Logic
8
8
RTFC
TOFC
E/210
TCBP
CTCSR
CTCR
Internal Peripheral Clock
(Ε)
To Interrupt
Logic
RTI
out
E / 212
POR
E/2
2
div
/4
E / 29
E / 214E / 213E / 212E / 211
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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