參數(shù)資料
型號(hào): HC05V7GRS
英文描述: 68HC05V7 General Release Specification
中文描述: 68HC05V7一般版本規(guī)范
文件頁數(shù): 69/170頁
文件大?。?/td> 980K
代理商: HC05V7GRS
SECTION 7: POWER SUPPLY AND REGULATION
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Page 55
The effect of not connecting the two V
DD
pins together is under evaluation and it is recom-
mended that they be connected at this time.
2) V
DD
to V
SSD
(pins 3 & 4): MCU internal digital power decoupling.
These pins are
connected to the on-chip regulator output via a small resistance. Decouple with a 0.1uF
ceramic or polystyrene capacitator. If the self-resonance frequency of the decoupling cir-
cuit (assume 4nH per bond wire) is too low, add a 0.01uF or smaller capacitor in parallel to
increase the bandwidth of the decoupling network. Ensure the smaller capacitor is located
closest to the V
DD
and V
SSD
pins.
3) V
CCA
to V
SSA1
and V
SSA2
: Analog subsystem power supply pins.
These pins are
internally isolated from the digital V
DD
and V
SS
supplies. The V
SSA1
pin provides a ground
return for the A/D subsystem. The V
SSA2
pin provides a ground return for the DLC sub-
system. The analog supply pins should be appropriately filtered to prevent any external
noise effecting the analog subsystems. The V
SSA1
and V
SSA2
pins should be brought
together with the digital ground at a single point which has a low (HF) impedance to
ground to prevent common mode noise problems. If this is not practical, then the V
SSA1
and V
SSA2
printed circuit board (PCB) traces should be routed in such a manner that digi-
tal ground return current is impeded from passing through the analog input ground refer-
ence as shown in the single sided PCB example below
.
V
SSD
V7
V
SSA
ANx
To System GND
AIN
GND
V
SSD
V7
V
SSA
ANx
AGND
AIN
Shielded cable,
Twisted pair, etc.
GND
Shielded cable, Twisted pair, etc.
Poor Analog Grounding
Better Analog Grounding
F
Freescale Semiconductor, Inc.
n
.
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