參數(shù)資料
型號： HC05V7GRS
英文描述： 68HC05V7 General Release Specification
中文描述： 68HC05V7一般版本規(guī)范
文件頁數(shù)： 25/170頁
文件大小： 980K
代理商： HC05V7GRS
SECTION 1: GENERAL DESCRIPTION
MOTOROLA
Page 11
1.5.7.3
External Clock
An external clock from another CMOS-compatible device can be connected to the OSC1
input. The OSC2 pin should be left unconnected, as shown in Figure 1-7(b).
1.5.8
RESET
This pin can be used as an input to reset the MCU to a known start-up state by pulling it to
the low state. The RESET pin contains an internal Schmitt trigger to improve its noise
immunity as an input. The RESET pin has an internal pulldown device that pulls the RESET
pin low when there is an internal COP Watchdog reset, POR, illegal address reset, a
disabled STOP instruction reset, or an internal low voltage reset. Refer to SECTION 6
RESETS.
1.5.9
IRQ (MASKABLE INTERRUPT REQUEST)
This input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ interrupt
function has a mask option to select either negative edge-sensitive triggering or both
negative edge-sensitive and low level-sensitive triggering. The IRQ input requires an
external resistor to V
DD
for “wire-OR” operation, if desired. If the IRQ pin is not used, it must
be tied to the V
DD
supply. The IRQ pin contains an internal Schmitt trigger as part of its input
to improve noise immunity. Each of the PA0 thru PA7 and PC0 thru PC7 I/O pins may be
connected as an OR function with the IRQ interrupt function. This capability allows
keyboard scan applications where the transitions on the I/O pins will behave the same as
the IRQ pin. The edge or level sensitivity selected by a mask option for the IRQ pin does
not apply to the I/O pin interrupt. The I/O pin interrupt is always negative edge sensitive.
See SECTION 5 INTERRUPTS for more details on the interrupts.
1.5.10
PA0-PA7
These eight I/O lines comprise Port A. The state of any pin is software programmable and
all Port A lines are configured as inputs during power-on or reset. All eight pins are
connected via an internal gate to the IRQ interrupt function. When the IRQ interrupt function
is enabled, all the Port A pins will act as negative edge sensitive IRQ sources. See
SECTION 9 PARALLEL I/O for more details on the I/O ports.
1.5.11
PB0-PB5, PB6/TCMP, PB7/TCAP
These eight I/O lines comprise Port B. The state of any pin is software programmable and
all Port B lines are configured as inputs during power-on or reset. See SECTION 9
PARALLEL I/O for more details on the I/O ports. PB6 and PB7 are also shared with timer
functions. The TCAP pin controls the input capture feature for the on-chip 16-bit timer. The
TCMP pin provides an output for the output compare feature of the on-chip 16-bit timer. See
SECTION 11 16-BIT TIMER for more details on the operation of the timer subsystem.
1.5.12
PC0-PC7
These eight I/O lines comprise Port C. The state of any pin is software programmable and
all Port C lines are configured as inputs during power-on or reset. All eight pins are
connected via an internal gate to the IRQ interrupt function. When the IRQ interrupt function
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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