- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371773 > HC05V7GRS 68HC05V7 General Release Specification PDF資料下載
參數(shù)資料
| 型號(hào)： | HC05V7GRS |
| 英文描述： | 68HC05V7 General Release Specification |
| 中文描述： | 68HC05V7一般版本規(guī)范 |
| 文件頁(yè)數(shù)： | 144/170頁(yè) |
| 文件大?。?/td> | 980K |
| 代理商： | HC05V7GRS |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)當(dāng)前第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)
MOTOROLA
Page 130
SECTION 15: MESSAGE DATA LINK CONTROLLER
MC68HC05V7 Specification Rev. 1.0
15.7.5
MDLC STOP MODE
This power conserving mode is automatically entered from the Run mode whenever the
CPU executes a STOP instruction, or if the CPU executes a WAIT instruction and the WCM
bit in the MCR register is previously set. This is the lowest power mode that the MDLC can
enter.
A subsequent passive to active transition on the J1850 bus will cause the MDLC to ’wake
up’ and generate a non-maskable CPU interrupt request. The MDLC
is not
guaranteed to
correctly receive the message which woke it up since it may take some time for the MDLC
internal operating clocks to restart and stabilize.
When MDLC Stop mode is entered, the analog circuitry within the transmitter will be put
into a power conserving ’sleep’ mode. In MDLC Stop mode the MDLC can neither do wave
shaping nor drive any data. Therefore, it is important that the programmer ensures that all
transmissions are complete or aborted before putting the MDLC into MDLC Stop mode.
If this mode is entered while the MDLC is receiving a message, the first subsequent
received edge will cause the MDLC to immediately wake up, generate a CPU interrupt
request, and wait for the MDLC internal operating clocks to restart and stabilize before
normal communication can resume. Therefore, the MDLC is not guaranteed to correctly
receive that message.
15.7.6
MDLC WAIT MODE
This power conserving mode is automatically entered from the Run mode whenever the
CPU executes a WAIT instruction and the WCM bit in the MCR register is previously clear.
A subsequent successfully received message, including one that is in progress at the time
that this mode is entered, will cause the MDLC to ’wake up’ and generate a CPU interrupt
request if the Interrupt Enable (IE) bit in the MCR register is previously set. This results in
less of a power saving, but the MDLC
is
guaranteed to correctly receive the message which
woke it up since the MDLC internal operating clocks are kept running.
When MDLC Wait mode is entered, the analog circuitry within the transmitter will be put into
a power conserving ’sleep’ mode. In MDLC Wait mode the MDLC can neither do wave
shaping nor drive any data. Therefore, it is important the programmer ensures that all
transmissions are complete or aborted before putting the MDLC into MDLC Stop or MDLC
Wait mode.
15.7.7
CONTROLLING EXTERNAL VOLTAGE REGULATORS
If the application node contains other, off-chip, supply voltage regulators that need to be
controlled by J1850 network activity then an output port pin of the MCU must be reserved
by the programmer for use as a Power Sense (PSEN) signal. This pin will provide a logical
indication of when the MDLC is active through software.
Whenever the MCU is in the normal (Run) mode of operation, the programmer should
assert
the PSEN output on the chosen port pin. The programmer should
negate
the PSEN
output just prior to placing the microcontroller in the Stop or Wait mode.
F
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HC05 | Bipolar Transistor; Transistor Polarity:Dual P Channel; Power Dissipation:20W; DC Current Gain Min (hfe):25; Collector Current:1A; DC Current Gain Max (hfe):200; Power (Ptot):20W |
| HC1-5502A-7 | Subscriber Line Interface Circuit |
| HC4P-5502A-7 | Subscriber Line Interface Circuit |
| HC1062A | Low Voltage Telephone Speech Transmission Circuit / High/Low Level Mute |
| HC1198 | Peripheral IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HC060WE1DS038B | 制造商:TE Connectivity 功能描述:EC7174-000 |
| HC060YW1DS038B | 制造商:TE Connectivity 功能描述:EC7207-000 |
| HC06B05000J0G | 制造商:FCI 功能描述:OEM ITEM 505-5BNF-SPRING CLAMP SYSTEM |
| HC08 | 制造商:Texas Instruments 功能描述: |
| HC08100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Breake Away Header .025(0.64mm) Square Posts |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。