
List of Figures
ix
21910D
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August 1999
AMD-751
System Controller Data Sheet
Preliminary Information
List of Figures
Figure 1.
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Figure 32.
AMD-750
Chipset System Block Diagram . . . . . . . . . . . . . . . 6
AMD-751
System Controller Block Diagram. . . . . . . . . . . . 12
AMD Athlon
Processor-Based System Clocking. . . . . . . . . 14
Ordering Information Elements . . . . . . . . . . . . . . . . . . . . . . . 15
System Memory View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Address Mapping for x86 Legacy . . . . . . . . . . . . . . . . . . . . . . 47
Block Diagram of the Bus Interface Unit (BIU). . . . . . . . . . .53
SIP Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
AMD Athlon
System Bus Data Buffers (BIU) . . . . . . . . . . . 58
Memory Request Organizer (MRO) Block Diagram . . . . . . . 60
Memory Queue Arbiter (MQA) Block Diagram . . . . . . . . . . . 61
Memory Controller (MCT) Block Diagram . . . . . . . . . . . . . . . 63
SDRAM Interface Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
DRAM Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Refresh Timer and Counters . . . . . . . . . . . . . . . . . . . . . . . . . .69
AMD-751
System Controller Clocking Scheme. . . . . . . . . .75
100-MHz SDRAM Detailed Timing . . . . . . . . . . . . . . . . . . . . . 76
AGP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
AGP Queues and Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
AMD-751
System Controller Arbiters . . . . . . . . . . . . . . . . . 91
Address Remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Cache Hierarchy (Conventional Two-Level Scheme) . . . . . . 96
Conventional GART Scheme
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Multiple Tables . . . . . . . . . . 96
Page Translation Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Page Directory Entry (PDE) Definition . . . . . . . . . . . . . . . . . 99
Address Translation Flow Chart . . . . . . . . . . . . . . . . . . . . . . 101
Two-Level GART Translation Scheme . . . . . . . . . . . . . . . . . 103
Another View Of the Two-Level Indexing Scheme . . . . . . . 104
Power Management Signal Connections. . . . . . . . . . . . . . . . 106
ACPI Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SYSCLK Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
CLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187