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參數(shù)資料
| 型號： | uPSD3251 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設(shè)備) |
| 中文描述： | 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核（帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設(shè)備） |
| 文件頁數(shù)： | 99/128頁 |
| 文件大?。?/td> | 1566K |
| 代理商： | UPSD3251 |
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μPSD3251F
Port Data Registers
The Port Data Registers, shown in Table 75, are
used by the MCU to write data to or read data from
the ports. Table 75 shows the register name, the
ports having each register type, and MCU access
for each register type. The registers are described
below.
Data In.
Port pins are connected directly to the
Data In buffer. In MCU I/O Input Mode, the pin in-
put is read through the Data In buffer.
Data Out Register.
Stores output data written by
the MCU in the MCU I/O Output Mode. The con-
tents of the Register are driven out to the pins if the
Direction Register or the output enable product
term is set to '1.' The contents of the register can
also be read back by the MCU.
Output Macrocells (OMC).
The CPLD Output
Macrocells (OMC) occupy a location in the MCU
’
s
address space. The MCU can read the output of
the Output Macrocells (OMC). If the OMC Mask
Register Bits are not set, writing to the macrocell
loads data to the macrocell flip-flops. See the sec-
tion entitled
“
PLDs,
”
page 88.
OMC Mask Register.
Each OMC Mask Register
Bit corresponds to an Output Macrocell (OMC) flip-
flop. When the OMC Mask Register Bit is set to a
'1,' loading data into the Output Macrocell (OMC)
flip-flop is blocked. The default value is '0' or un-
blocked.
Input Macrocells (IMC).
The Input Macrocells
(IMC) can be used to latch or store external inputs.
The outputs of the Input Macrocells (IMC) are rout-
ed to the PLD input bus, and can be read by the
MCU. See the section entitled
“
PLDs,
”
page 88.
Enable Out.
The Enable Out register can be read
by the MCU. It contains the output enable values
for a given port. A '1' indicates the driver is in out-
put mode. A '0' indicates the driver is in tri-state
and the pin is in input mode.
Table 74. Drive Register Pin Assignment
Note: 1. NA = Not Applicable.
Table 75. Port Data Registers
Drive
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port B
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port C
Open
Drain
NA
(1)
NA
(1)
Open
Drain
Open
Drain
Open
Drain
NA
(1)
NA
(1)
Port D
NA
(1)
NA
(1)
NA
(1)
NA
(1)
NA
(1)
Slew
Rate
Slew
Rate
NA
(1)
Register Name
Port
MCU Access
Data In
B, C, D
READ
–
input on pin
Data Out
B, C, D
WRITE/READ
Output Macrocell
B, C
READ
–
outputs of macrocells
WRITE
–
loading macrocells flip-flop
Mask Macrocell
B, C
WRITE/READ
–
prevents loading into a given
macrocell
Input Macrocell
B, C
READ
–
outputs of the Input Macrocells
Enable Out
B, C
READ
–
the output enable control of the port driver
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