參數(shù)資料
型號(hào): uPSD3251
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設(shè)備)
中文描述: 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核(帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設(shè)備)
文件頁數(shù): 115/128頁
文件大?。?/td> 1566K
代理商: UPSD3251
115/128
μPSD3251F
Note: 1. I
PD
(Power-down Mode) is measured with:
XTAL1=V
SS
; XTAL2=not connected; RESET=V
CC
; all other pins are disconnected. PLD not in Turbo Mode.
2. I
CC_CPU
(active mode) is measured with:
XTAL1 driven with t
CLCH
, t
CHCL
= 5ns, V
IL
= V
SS
+0.5V, V
IH
= Vcc
0.5V, XTAL2 = not connected; RESET=V
SS
; all other pins are
disconnected. I
CC
would be slightly higher if a crystal oscillator is used (approximately 1mA).
3. I
CC_CPU
(Idle Mode) is measured with:
XTAL1 driven with t
CLCH
, t
CHCL
= 5ns, V
IL
= V
SS
+0.5V, V
IH
= V
CC
0.5V, XTAL2 = not connected; RESET=V
CC
; all other pins are
disconnected.
4. See Figure 56 for the PLD current calculation.
5. I/O current = 0 mA, all I/O pins are disconnected.
I
RST
Reset Pin Pull-up Current
(RESET)
V
IN
= V
SS
10
55
μA
I
FR
XTAL Feedback Resistor
Current (XTAL1)
XTAL1 = V
CC
XTAL2 = V
SS
20
50
μA
I
LI
Input Leakage Current
V
SS
< V
IN
< V
CC
1
1
μA
I
LO
Output Leakage Current
0.45 < V
OUT
< V
CC
10
10
μA
I
PD(1)
Power-down Mode
V
CC
= 5.5V
LVD logic disabled
250
μA
LVD logic enabled
380
μA
I
CC_CPU(2,3,5)
Active (12MHz)
V
CC
= 5V
20
30
mA
Idle (12MHz)
8
10
mA
Active (24MHz)
V
CC
= 5V
30
38
mA
Idle (24MHz)
15
20
mA
Active (40MHz)
V
CC
= 5V
40
62
mA
Idle (40MHz)
20
30
mA
I
CC_PSD
(DC)
(5)
Operating
Supply Current
PLD Only
PLD_TURBO = Off,
f = 0MHz
(4)
0
μA/PT
(5)
PLD_TURBO = On,
f = 0MHz
400
700
μA/PT
Flash
memory
During Flash memory
WRITE/Erase Only
15
30
mA
Read only, f = 0MHz
0
0
mA
SRAM
f = 0MHz
0
0
mA
I
CC_PSD
(AC)
(5)
PLD AC Base
Note 4
Flash memory AC Adder
2.5
3.5
mA/
MHz
SRAM AC Adder
1.5
3.0
mA/
MHz
Symbol
Parameter
Test Condition
(in addition to those
in Table 84, page 112)
Min.
Typ.
Max.
Unit
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