參數(shù)資料
型號: uPSD3251
廠商: 意法半導體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設備)
中文描述: 閃存可編程系統(tǒng)設備與8032微控制器內(nèi)核(帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設備)
文件頁數(shù): 35/128頁
文件大?。?/td> 1566K
代理商: UPSD3251
35/128
μPSD3251F
INTERRUPT SYSTEM
There are interrupt requests from 10 sources as
follows (see Figure 14, page 36).
I
INT0 External Interrupt
I
2nd USART Interrupt
I
Timer 0 Interrupt
I
I
2
C Interrupt
I
INT1 External Interrupt (or ADC Interrupt)
I
Timer 1 Interrupt
I
USART Interrupt
I
Timer 2 Interrupt
External Int0
The INT0 can be either level-active or transition-
active depending on Bit IT0 in register TCON.
The flag that actually generates this interrupt is
Bit IE0 in TCON.
When an external interrupt is generated, the
corresponding request flag is cleared by the
hardware when the service routine is vectored
to only if the interrupt was transition activated.
If the interrupt was level activated then the inter-
rupt request flag remains set until the requested
interrupt is actually generated. Then it has to de-
activate the request before the interrupt service
routine is completed, or else another interrupt
will be generated.
Timer 0 and 1 Interrupts
Timer 0 and Timer 1 Interrupts are generated by
TF0 and TF1 which are set by an overflow of
their respective Timer/Counter registers (except
for Timer 0 in Mode 3).
These flags are cleared by the internal hard-
ware when the interrupt is serviced.
Timer 2 Interrupt
Timer 2 Interrupt is generated by TF2 which is
set by an overflow of Timer 2. This flag has to be
cleared by the software - not by hardware.
It is also generated by the T2EX signal (Timer 2
External Interrupt P1.1) which is controlled by
EXEN2 and EXF2 Bits in the T2CON register.
I
2
C Interrupt
The interrupt of the I
2
C is generated by Bit INTR
in the register S2STA.
This flag is cleared by hardware.
External Int1
The INT1 can be either level active or transition
active depending on Bit IT1 in register TCON.
The flag that actually generates this interrupt is
Bit IE1 in TCON.
When an external interrupt is generated, the
corresponding request flag is cleared by the
hardware when the service routine is vectored
to only if the interrupt was transition activated.
If the interrupt was level activated then the inter-
rupt request flag remains set until the requested
interrupt is actually generated. Then it has to de-
activate the request before the interrupt service
routine is completed, or else another interrupt
will be generated.
The ADC can take over the External INT1 to
generate an interrupt on conversion being com-
pleted
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