參數(shù)資料
型號： uPSD3251
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設(shè)備)
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核（帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設(shè)備）
文件頁數(shù)： 117/128頁
文件大?。?/td> 1566K
代理商： UPSD3251
117/128
μPSD3251F
Figure 58. Input to Output Disable / Enable
Table 89. CPLD Combinatorial Timing (5V Device)
Note: 1. Fast Slew Rate output available on PB3-PB0 and PD1. Decrement times by given amount.
2. t
PD
for MCU address and control signals refers to delay from pins on MCU Bus to CPLD combinatorial output.
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Slew
rate
(1)
Unit
t
PD(2)
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
20
+ 2
+ 10
–
2
ns
t
EA
CPLD Input to CPLD Output
Enable
21
+ 10
–
2
ns
t
ER
CPLD Input to CPLD Output
Disable
21
+ 10
–
2
ns
t
ARP
CPLD Register Clear or Preset
Delay
21
+ 10
–
2
ns
t
ARPW
CPLD Register Clear or Preset
Pulse Width
10
+ 10
ns
t
ARD
CPLD Array Delay
Any
macrocell
11
+ 2
ns
tER
tEA
INPUT
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
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參數(shù)描述
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