參數(shù)資料
型號： uPSD3251
廠商： 意法半導體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內核的Flash可編程系統(tǒng)設備)
中文描述： 閃存可編程系統(tǒng)設備與8032微控制器內核（帶8032微控制器內核的閃存可編程系統(tǒng)設備）
文件頁數(shù)： 40/128頁
文件大?。?/td> 1566K
代理商： UPSD3251
μPSD3251F
40/128
POWER-SAVING MODE
Two software selectable modes of reduced power
consumption are implemented (see Table 25).
Idle Mode
The following Functions are Switched Off.
–
CPU (Halted)
The following Function Remain Active During Idle
Mode.
–
External Interrupts
–
Timer 0, Timer 1, Timer 2
–
USART
–
8-bit ADC
–
I
2
C Interface
Note:
Interrupt or RESET terminates the Idle
Mode.
Power-Down Mode
–
System Clock Halted
–
LVD Logic Remains Active
–
SRAM contents remains unchanged
–
The SFRs retain their value until a RESET is as-
serted
Note:
The only way to exit Power-down Mode is a
RESET.
Power Control Register
The Idle and Power-down Modes are activated by
software via the PCON register (see Tables 26
and Table 27, page 41).
Idle Mode
The instruction that sets PCON.0 is the last in-
struction executed in the normal operating mode
before Idle Mode is activated. Once in the Idle
Mode, the CPU status is preserved in its entirety:
Stack pointer, Program counter, Program status
word, Accumulator, RAM and All other registers
maintain their data during Idle Mode.
There are three ways to terminate the Idle Mode.
–
Activation of any enabled interrupt will cause
PCON.0 to be cleared by hardware terminating
Idle mode. The interrupt is serviced, and follow-
ing return from interrupt instruction RETI, the
next instruction to be executed will be the one
which follows the instruction that wrote a logic '1'
to PCON.0.
–
External hardware reset: the hardware reset is
required to be active for two machine cycle to
complete the RESET operation.
–
Internal reset: the microcontroller restarts after
3 machine cycles in all cases.
Power-Down Mode
The instruction that sets PCON.1 is the last exe-
cuted prior to going into the Power-down Mode.
Once in Power-down Mode, the oscillator is
stopped. The contents of the on-chip RAM and the
Special Function Register are preserved.
The Power-down Mode can be terminated by an
external RESET.
Table 25. Power-Saving Mode Power Consumption
Table 26. Pin Status During Idle and Power-down Mode
Mode
Addr/Data
Ports1,3,4
I
2
C
Idle
Maintain Data
Maintain Data
Active
Power-down
Maintain Data
Maintain Data
Disable
SFR
Addr
Reg
Name
Bit Register Name
ValueComments
7
6
5
4
3
2
1
0
87
PCON
SMOD
SMOD1
LVREN ADSFINT RCLK1
TCLK1
PD
IDLE
00
Power Ctrl
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相關代理商/技術參數(shù)
參數(shù)描述
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