參數(shù)資料
型號： uPSD3251
廠商： 意法半導體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設備)
中文描述： 閃存可編程系統(tǒng)設備與8032微控制器內(nèi)核（帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設備）
文件頁數(shù)： 84/128頁
文件大?。?/td> 1566K
代理商： UPSD3251
μPSD3251F
84/128
SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to two product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to Voltage Standby (V
STBY
, PC2). If you have an
external battery connected to the μPSD3200, the
contents of the SRAM are retained in the event of
a power loss. The contents of the SRAM are re-
tained so long as the battery voltage remains at 2V
or greater. If the supply voltage falls below the bat-
tery voltage, an internal power switchover to the
battery occurs.
PC4 can be configured as an output that indicates
when power is being drawn from the external bat-
tery. Battery-on Indicator (V
BATON
, PC4) is High
with the supply voltage falls below the battery volt-
age and the battery on Voltage Standby (V
STBY
,
PC2) is supplying power to the internal SRAM.
SRAM Select (RS0), Voltage Standby (V
STBY
,
PC2) and Battery-on Indicator (V
BATON
, PC4) are
all configured using PSDsoft Express Configura-
tion.
Sector Select and SRAM Select
Sector Select (FS0-FS3, CSBOOT0-CSBOOT1)
and SRAM Select (RS0) are all outputs of the
DPLD. They are setup by writing equations for
them in PSDsoft Express. The following rules ap-
ply to the equations for these signals:
1. Primary Flash memory and secondary Flash
memory Sector Select signals must
not
be larg-
er than the physical sector size.
2. Any primary Flash memory sector must
not
be
mapped in the same memory space as another
Flash memory sector.
3. A secondary Flash memory sector must
not
be
mapped in the same memory space as another
secondary Flash memory sector.
4. SRAM and I/O must
not
overlap.
5. A secondary Flash memory sector
may
overlap
a primary Flash memory sector. In case of over-
lap, priority is given to the secondary Flash
memory sector.
6. SRAM and I/O
may
overlap any other memory
sector. Priority is given to the SRAM or I/O.
Example.
FS0 is valid when the address is in the
range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to
87FFh. Any address in the range of RS0 always
accesses the SRAM. Any address in the range of
CSBOOT0 greater than 87FFh (and less than
9FFFh) automatically addresses secondary Flash
memory segment 0. Any address greater than
9FFFh accesses the primary Flash memory seg-
ment 0. You can see that half of the primary Flash
memory segment 0 and one-fourth of secondary
Flash memory segment 0 cannot be accessed in
this example.
Note:
An equation that defined FS1 to anywhere
in the range of 8000h to BFFFh would
not
be valid.
Figure 39 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must
not
overlap. Level one has the highest priority and
level 3 has the lowest.
Figure 39. Priority Level of Memory and I/O
Components in the PSD Module
Level 1
SRAM or I/O
Level 2
Secondary
Non-Volatile Memory
Level 3
Primary Flash Memory
AI07865
Lowest Priority
Highest Priority
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相關代理商/技術參數(shù)
參數(shù)描述
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UPSD3253A-24T1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3253A-24T6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
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