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參數(shù)資料
| 型號： | uPSD3251 |
| 廠商： | 意法半導體 |
| 英文描述： | Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設(shè)備) |
| 中文描述： | 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核（帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設(shè)備） |
| 文件頁數(shù)： | 97/128頁 |
| 文件大?。?/td> | 1566K |
| 代理商： | UPSD3251 |
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μPSD3251F
Table 67. Port Operating Modes
Note: 1. JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins.
2. On pins PC2, PC3, PC4 and PC7 only.
Table 68. Port Operating Mode Settings
Note: N/A = Not Applicable
1. The direction of the Port B, C, and D pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array.
Table 69. I/O Port Latched Address Output Assignments
Port Configuration Registers (PCR)
Each Port has a set of Port Configuration Regis-
ters (PCR) used for configuration. The contents of
the registers can be accessed by the MCU through
normal READ/WRITE bus cycles at the addresses
given in Table 59. The addresses in Table 59 are
the offsets in hexadecimal from the base of the
CSIOP register.
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, Bit 0 in a register refers to Bit 0 of its
port. The three Port Configuration Registers
(PCR), shown in Table 70, are used for setting the
Port configurations. The default Power-up state for
each register in Table 70 is 00h.
Control Register.
Any bit reset to '0' in the Con-
trol Register sets the corresponding port pin to
MCU I/O Mode, and a '1' sets it to Address Out
Mode. The default mode is MCU I/O. Only Port B
has an associated Control Register.
Direction Register.
The Direction Register, in
conjunction with the output enable (except for Port
D), controls the direction of data flow in the I/O
Ports. Any bit set to '1' in the Direction Register
causes the corresponding pin to be an output, and
any bit set to '0' causes it to be an input. The de-
fault mode for all port pins is input.
Figure 49, page 100 and Figure 50, page 101
show the Port Architecture diagrams for Ports B
and C, respectively. The direction of data flow for
Ports B, and C are controlled not only by the direc-
tion register, but also by the output enable product
term from the PLD AND Array. If the output enable
product term is not active, the Direction Register
has sole control of a given pin
’
s direction.
An example of a configuration for a Port with the
three least significant bits set to output and the re-
mainder set to input is shown in Table 73. Since
Port D only contains one pin (shown in Figure 52),
the Direction Register for Port D has only one bit
active.
Port Mode
Port B
Port C
Port D
MCU I/O
Yes
Yes
Yes
PLD I/O
McellAB Outputs
McellBC Outputs
Additional Ext. CS Outputs
PLD Inputs
Yes
Yes
No
Yes
No
Yes
(3)
No
Yes
No
No
Yes
Yes
Address Out
Yes (A7
–
0)
No
No
JTAG ISP
No
Yes
(1)
No
Mode
Defined in PSDsoft
Control Register
Setting
Direction Register
Setting
VM Register Setting
MCU I/O
Declare pins only
0
1 = output,
0 = input (Note 1)
N/A
PLD I/O
Logic equations
N/A
(Note
1)
N/A
Address Out (Port B)
Declare pins only
1
1 (Note 1)
N/A
Port B (PB3-PB0)
Port B (PB7-PB4)
Address a3-a0
Address a7-a4
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