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參數(shù)資料
| 型號： | uPSD3251 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設(shè)備) |
| 中文描述： | 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核（帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設(shè)備） |
| 文件頁數(shù)： | 104/128頁 |
| 文件大?。?/td> | 1566K |
| 代理商： | UPSD3251 |
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μPSD3251F
104/128
POWER MANAGEMENT
All PSD Module offers configurable power saving
options. These options may be used individually or
in combinations, as follows:
I
The primary and secondary Flash memory, and
SRAM blocks are built with power management
technology. In addition to using special silicon
design methodology, power management
technology puts the memories into Standby
Mode when address/data inputs are not
changing (zero DC current). As soon as a
transition occurs on an input, the affected
memory
“
wakes up,
”
changes and latches its
outputs, then goes back to standby. The
designer does
not
have to do anything special to
achieve Memory Standby Mode when no inputs
are changing
—
it happens automatically.
The PLD sections can also achieve Standby
Mode when its inputs are not changing, as de-
scribed in the sections on the Power Manage-
ment Mode Registers (PMMR).
I
As with the Power Management Mode, the
Automatic Power Down (APD) block allows the
PSD Module to reduce to standby current
automatically. The APD Unit can also block
MCU address/data signals from reaching the
memories and PLDs. The APD Unit is described
in more detail in the sections entitled
“
POWER
MANAGEMENT
”
page 104.
Built in logic monitors the Address Strobe of the
MCU for activity. If there is no activity for a cer-
tain time period (MCU is asleep), the APD Unit
initiates Power-down Mode (if enabled). Once in
Power-down Mode, all address/data signals are
blocked from reaching memory and PLDs, and
the memories are deselected internally. This al-
lows the memory and PLDs to remain in
Standby Mode even if the address/data signals
are changing state externally (noise, other de-
vices on the MCU bus, etc.). Keep in mind that
any unblocked PLD input signals that are
changing states keeps the PLD out of Standby
Mode, but not the memories.
I
The PMMRs can be written by the MCU at run-
time to manage power. The PSD Module
supports
“
blocking bits
”
in these registers that
are set to block designated signals from
reaching both PLDs. Current consumption of
the PLDs is directly related to the composite
frequency of the changes on their inputs (see
Figure 56). Significant power savings can be
achieved by blocking signals that are not used
in DPLD or CPLD logic equations.
Figure 53. APD Unit
The PSD Module has a Turbo Bit in PMMR0. This
bit can be set to turn the Turbo Mode off (the de-
fault is with Turbo Mode turned on). While Turbo
Mode is off, the PLDs can achieve standby current
when no PLD inputs are changing (zero DC cur-
rent). Even when inputs do change, significant
power can be saved at lower frequencies (AC cur-
rent), compared to when Turbo Mode is on. When
the Turbo Mode is on, there is a significant DC cur-
rent component and the AC component is higher.
Automatic Power-down (APD) Unit and Power-
down Mode.
The APD Unit, shown in Figure 53,
puts the PSD Module into Power-down Mode by
monitoring the activity of Address Strobe (ALE). If
the APD Unit is enabled, as soon as activity on Ad-
dress Strobe (ALE) stops, a four-bit counter starts
counting. If Address Strobe (ALE/AS) remains in-
active for fifteen clock periods of CLKIN (PD1),
Power-down (PDN) goes High, and the PSD Mod-
ule enters Power-down Mode, as discussed next.
APD EN
PMMR0 BIT 1=1
ALE
RESET
CLKIN
TRANSITION
DETECTION
EDGE
DETECT
APD
COUNTER
POWER DOWN
(PDN)
SELECT
DISABLE BUS
INTERFACE
CSIOP SELECT
FLASH SELECT
SRAM SELECT
PD
CLR
PD
PLD
AI07870
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