參數(shù)資料
型號(hào)： uPSD3251
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設(shè)備)
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核（帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設(shè)備）
文件頁數(shù)： 46/128頁
文件大?。?/td> 1566K
代理商： UPSD3251
μPSD3251F
46/128
WATCHDOG TIMER
The hardware Watchdog Timer (WDT) resets the
μPSD3251F device when it overflows. The WDT is
intended as a recovery method in situations where
the CPU may be subjected to a software upset. To
prevent a system reset the timer must be reloaded
in time by the application software. If the processor
suffers a hardware/software malfunction, the soft-
ware will fail to reload the timer. This failure will re-
sult in a reset upon overflow thus preventing the
processor running out of control.
In the Idle Mode the watchdog timer and reset cir-
cuitry remain active. The WDT consists of a 22-bit
counter, the Watchdog Timer RESET (WDRST)
SFR and Watchdog Key Register (WDKEY).
Since the WDT is automatically enabled while the
processor is running. the user only needs to be
concerned with servicing it.
The 22-bit counter overflows when it reaches
4194304 (3FFFFFH). The WDT increments once
every machine cycle.
This means the user must reset the WDT at least
every 4194304 machine cycles (1.258 seconds at
40MHz). To reset the WDT the user must write a
value between 00-7EH to the WDRST register.
The value that is written to the WDRST is loaded
to the 7MSB of the 22-bit counter. This allows the
user to pre-loaded the counter to an initial value to
generate a flexible Watchdog time out period.
Writing a
“
00
”
to WDRST clears the counter.
The watchdog timer is controlled by the watchdog
key register, WDKEY. Only pattern 01010101
(=55H), disables the watchdog timer. The rest of
pattern combinations will keep the watchdog timer
enabled. This security key will prevent the watch-
dog timer from being terminated abnormally when
the function of the watchdog timer is needed.
In Idle Mode, the oscillator continues to run. To
prevent the WDT from resetting the processor
while in Idle, the user should always set up a timer
that will periodically exit Idle, service the WDT, and
re-enter Idle Mode.
Watchdog reset pulse width depends on the clock
frequency (see Figure 19, page 47). The reset pe-
riod is Tf
OSC
x 12 x 2
22
.
The RESET pulse width is Tf
OSC
x 12 x 2
15
.
Table 31. Watchdog Timer Key Register (WDKEY: 0AEH)
Table 32. Description of the WDKEY Bits
Table 33. Watchdog Timer Clear Register (WDRST: 0A6H)
Table 34. Description of the WDRST Bits
Note: The Watchdog Timer (WDT) is enabled at power-up or reset and must be served or disabled.
7
6
5
4
3
2
1
0
WDKEY7
WDKEY6
WDKEY5
WDKEY4
WDKEY3
WDKEY2
WDKEY1
WDKEY0
Bit
Symbol
Function
7 to 0
WDKEY7 to
WDKEY0
Enable or disable Watchdog Timer.
01010101 (=55h): disable watchdog timer. Others: enable watchdog timer
7
6
5
4
3
2
1
0
Reserved
WDRST6
WDRST5
WDRST4
WDRST3
WDRST2
WDRST1
WDRST0
Bit
Symbol
Function
7
—
Reserved
6 to 0
WDRST6 to
WDRST0
To reset Watchdog Timer, write any value beteen 00h and 7Eh to this register.
This value is loaded to the 7 most significant bits of the 22-bit counter.
For example: MOV WDRST,#1EH
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