參數(shù)資料
型號(hào)： uPSD3251
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設(shè)備)
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核（帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設(shè)備）
文件頁(yè)數(shù)： 96/128頁(yè)
文件大?。?/td> 1566K
代理商： UPSD3251
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μPSD3251F
96/128
The Port pin
’
s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs are not defined
and that port pin is not defined as a CPLD output
in the PSDsoft, then the Direction Register has
sole control of the buffer that drives the port pin.
The contents of these registers can be altered by
the MCU. The Port Data Buffer (PDB) feedback
path allows the MCU to check the contents of the
registers.
Ports B and C have embedded Input Macrocells
(IMC). The Input Macrocells (IMC) can be config-
ured as latches, registers, or direct inputs to the
PLDs. The latches and registers are clocked by
Address Strobe (ALE) or a product term from the
PLD AND Array. The outputs from the Input Mac-
rocells (IMC) drive the PLD input bus and can be
read by the MCU. See the section entitled
“
Input
Macrocell,
”
page 94.
Port Operating Modes
The I/O Ports have several modes of operation.
Some modes can be defined using PSDsoft, some
by the MCU writing to the Control Registers in
CSIOP space, and some by both. The modes that
can only be defined using PSDsoft must be pro-
grammed into the device and cannot be changed
unless the device is reprogrammed. The modes
that can be changed by the MCU can be done so
dynamically at run-time. The PLD I/O, Data Port,
and Address Input Modes are the only modes that
must be defined before programming the device.
All other modes can be changed by the MCU at
run-time. See Application Note
AN1171
for more
detail.
Table 67 summarizes which modes are available
on each port. Table 70 shows how and where the
different modes are configured. Each of the port
operating modes are described in the following
sections.
MCU I/O Mode
In the MCU I/O Mode, the MCU uses the I/O Ports
block to expand its own I/O ports. By setting up the
CSIOP space, the ports on the PSD Module are
mapped into the MCU address space. The ad-
dresses of the ports are listed in Table 59.
A port pin can be put into MCU I/O Mode by writing
a '0' to the corresponding bit in the Control Regis-
ter. The MCU I/O direction may be changed by
writing to the corresponding bit in the Direction
Register, or by the output enable product term.
When the pin is configured as an output, the con-
tent of the Data Out Register drives the pin. When
configured as an input, the MCU can read the port
input through the Data In buffer. See Figure 48,
page 95.
Ports C and D do not have Control Registers, and
are in MCU I/O Mode by default. They can be used
for PLD I/O if equations are written for them in PS-
Dabel.
PLD I/O Mode
The PLD I/O Mode uses a port as an input to the
CPLD
’
s Input Macrocells (IMC), and/or as an out-
put from the CPLD
’
s Output Macrocells (OMC).
The output can be tri-stated with a control signal.
This output enable control signal can be defined
by a product term from the PLD, or by resetting the
corresponding bit in the Direction Register to '0.'
The corresponding bit in the Direction Register
must not be set to '1' if the pin is defined for a PLD
input signal in PSDsoft. The PLD I/O Mode is
specified in PSDsoft by declaring the port pins,
and then writing an equation assigning the PLD I/
O to a port.
Address Out Mode
Address Out Mode can be used to drive latched
MCU addresses on to the port pins. These port
pins can, in turn, drive external devices. Either the
output enable or the corresponding bits of both the
Direction Register and Control Register must be
set to a '1' for pins to use Address Out Mode. This
must be done by the MCU at run-time. See Table
69 for the address output pin assignments on Port
B.
JTAG In-System Programming (ISP)
Port C is JTAG compliant, and can be used for In-
System Programming (ISP). For more information
on the JTAG Port, see the section entitled
“
PRO-
GRAMMING IN-CIRCUIT USING THE JTAG SE-
RIAL INTERFACE,
”
page 109.
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