參數(shù)資料
型號： uPSD3251
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設(shè)備)
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核（帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設(shè)備）
文件頁數(shù)： 66/128頁
文件大小： 1566K
代理商： UPSD3251
μPSD3251F
66/128
I
2
C INTERFACE
The serial port supports the twin line I
2
C-bus, con-
sisting of a data line (SDA1), and a clock line
(SCL1) as shown in Figure 34. Depending on the
configuration, the SDA1 and SCL1 lines may re-
quire pull-up resistors.
These lines also function as I/O port lines if the I
2
C
bus is not enabled.
The system is unique because data transport,
clock generation, address recognition, and bus
control arbitration are all controlled by hardware.
The I
2
C serial I/O has complete autonomy in byte
handling and operates in 4 modes.
I
Master transmitter
I
Master receiver
I
Slave transmitter
I
Slave receiver
These functions are controlled by the SFRs (see
Tables 48, 49, and Table 50, page 67):
–
S2CON: the control of byte handling and the op-
eration of 4 mode.
–
S2STA: the contents of its register may also be
used as a vector to various service routines.
–
S2DAT: data shift register.
–
S2ADR: slave address register. Slave address
recognition is performed by On-Chip H/W.
Figure 34. Block Diagram of the I
2
C Bus Serial I/O
AI07430
SCL1
SDA1
Bus Clock Generator
Arbitration and Sync. Logic
Shift Register
Status Register
7
0
Slave Address
7
0
Control Register
7
0
7
0
I
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