參數(shù)資料
型號： uPSD3251
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設(shè)備)
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核（帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設(shè)備）
文件頁數(shù)： 118/128頁
文件大?。?/td> 1566K
代理商： UPSD3251
μPSD3251F
118/128
Figure 59. Synchronous Clock Mode Timing
–
PLD
Table 90. CPLD Macrocell Synchronous Clock Mode Timing (5V Device)
Note: 1. Fast Slew Rate output available on PB3-PB0 and PD1. Decrement times by given amount.
2. CLKIN (PD1) t
CLCL
= t
CH
+ t
CL
.
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Slew
rate
(1)
Unit
f
MAX
Maximum Frequency
External Feedback
1/(t
S
+t
CO
)
40.0
MHz
Maximum Frequency
Internal Feedback (f
CNT
)
1/(t
S
+t
CO
–
10)
66.6
MHz
Maximum Frequency
Pipelined Data
1/(t
CH
+t
CL
)
83.3
MHz
t
S
Input Setup Time
12
+ 2
+ 10
ns
t
H
Input Hold Time
0
ns
t
CH
Clock High Time
Clock Input
6
ns
t
CL
Clock Low Time
Clock Input
6
ns
t
CO
Clock to Output Delay
Clock Input
13
–
2
ns
t
ARD
CPLD Array Delay
Any
macrocell
11
+ 2
ns
t
MIN
Minimum Clock Period
(2)
t
CH
+t
CL
12
ns
tCH
tCL
tCO
tH
tS
CLKIN
INPUT
REGISTERED
OUTPUT
AI02860
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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