參數(shù)資料
型號(hào)： uPSD3251
廠(chǎng)商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設(shè)備)
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核（帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設(shè)備）
文件頁(yè)數(shù)： 45/128頁(yè)
文件大?。?/td> 1566K
代理商： UPSD3251
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μPSD3251F
SUPERVISORY
There are three ways to invoke a reset and initial-
ize the μPSD3251F device:
I
Via the external RESET pin
I
Via the internal LVR Block.
I
Via Watch Dog timer
The RESET mechanism is illustrated in Figure 18.
Each RESET source will cause an internal reset
signal active. The CPU responds by executing an
internal reset and puts the internal registers in a
defined state. This internal reset is also routed as
an active low reset input to the PSD Module.
External Reset
The RESET pin is connected to a Schmitt trigger
for noise reduction. A RESET is accomplished by
holding the RESET pin LOW for at least 1ms at
power up while the oscillator is running. Refer to
AC spec on other RESET timing requirements.
Low V
DD
Voltage Reset
An internal reset is generated by the LVR circuit
when the V
DD
drops below the reset threshold. Af-
ter V
DD
reaching back up to the reset threshold,
the RESET signal will remain asserted for 10ms
before it is released. On initial power-up the LVR
is enabled (default). After power-up the LVR can
be disabled via the LVREN Bit in the PCON Reg-
ister.
Note:
The LVR logic is still functional in both the
Idle and Power-down Modes.
The reset threshold:
I
5V operation: 4V +/- 0.25V
This logic supports approximately 0.1V of hystere-
sis and 1μs noise-cancelling delay.
Watchdog Timer Overflow
The Watchdog Timer generates an internal reset
when its 22-bit counter overflows. See WATCH-
DOG TIMER, page 46 for details.
Figure 18. RESET Configuration
AI07429
Reset
CPU
&
PERI.
Noise
Cancel
LVR
S
Q
R
CPU
Clock
Sync
10ms
Timer
WDT
PSD_RST
"Active Low"
10ms at 40Mhz
50ms at 8Mhz
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參數(shù)描述
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