參數(shù)資料
型號： uPSD3251
廠商： 意法半導體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設備)
中文描述： 閃存可編程系統(tǒng)設備與8032微控制器內(nèi)核（帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設備）
文件頁數(shù)： 16/128頁
文件大?。?/td> 1566K
代理商： UPSD3251
μPSD3251F
16/128
Figure 7. PSW (Program Status Word) Register
Program Memory
The program memory consists of two Flash mem-
ory: 64KByte Main Flash and 16KByte of Second-
ary Flash. The Flash memory can be mapped to
any address space as defined by the user in the
PSDsoft Tool. It can also be mapped to Data
memory space during Flash memory update or
programming.
After reset, the CPU begins execution from loca-
tion 0000h. As shown in Figure 8, each interrupt is
assigned a fixed location in Program Memory. The
interrupt causes the CPU to jump to that location,
where it commences execution of the service rou-
tine. External Interrupt 0, for example, is assigned
to location 0003h. If External Interrupt 0 is going to
be used, its service routine must begin at location
0003h. If the interrupt is not going to be used, its
service location is available as general purpose
Program Memory.
The interrupt service locations are spaced at 8-
byte intervals: 0003h for External Interrupt 0,
000Bh for Timer 0, 0013h for External Interrupt 1,
001Bh for Timer 1 and so forth. If an interrupt ser-
vice routine is short enough (as is often the case
in control applications), it can reside entirely within
that 8-byte interval (see Figure 8). Longer service
routines can use a jump instruction to skip over
subsequent interrupt locations, if other interrupts
are in use.
Data memory
The internal data memory is divided into four phys-
ically separated blocks: 256 bytes of internal RAM,
128 bytes of Special Function Registers (SFRs)
areas and 2K bytes (XRAM-PSD) in the PSD Mod-
ule.
RAM
Four register banks, each 8 registers wide, occupy
locations 0 through 31 in the lower RAM area.
Only one of these banks may be enabled at a time.
The next 16 bytes, locations 32 through 47, con-
tain 128 directly addressable bit locations. The
stack depth is only limited by the available internal
RAM space of 256 bytes.
XRAM-PSD
The 2K bytes of XRAM-PSD resides in the PSD
Module and can be mapped to any address space
through the DPLD (Decoding PLD) as defined by
the user in PSDsoft Development tool. The XRAM-
PSD has a battery backup feature that allow the
data to be retained in the event of a power lost.
The battery is connected to the Port C PC2 pin.
This pin must be configured in PSDSoft to be bat-
tery back-up.
Figure 8. Interrupt Location of Program
Memory
AI06639
CY
Reset Value 00h
Parity Flag
Bit not assigned
Overflow Flag
Register Bank Select Flags
(to select Bank0-3)
Carry Flag
Auxillary Carry Flag
General Purpose Flag
AC FO RS1 RS0 OV
P
MSB
LSB
PSW
AI06640
0000h
Reset
8 Bytes
Interrupt
Location
0003h
000Bh
0013h
008Bh
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相關代理商/技術參數(shù)
參數(shù)描述
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