參數(shù)資料
型號： uPSD3251
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設(shè)備)
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核（帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設(shè)備）
文件頁數(shù)： 121/128頁
文件大小： 1566K
代理商： UPSD3251
121/128
μPSD3251F
Figure 63. Reset (RESET) Timing
Table 94. Reset (RESET) Timing (5V Device)
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
Table 95. V
STBYON
Definitions Timing (5V Device)
Symbol
Note: 1. V
STBYON
timing is measured at V
CC
ramp rate of 2ms.
Symbol
Parameter
Conditions
Min
Max
Unit
t
NLNH
RESET Active Low Time
(1)
150
ns
t
NLNH
–
PO
Power-on Reset Active Low Time
1
ms
t
OPR
RESET High to Operational Device
120
ns
Parameter
Conditions
Min
Typ
Max
Unit
t
BVBH
V
STBY
Detection to V
STBYON
Output High
(Note
1)
20
μs
t
BXBL
V
STBY
Off Detection to V
STBYON
Output
Low
(Note
1)
20
μs
tNLNH-PO
Power-On Reset
tOPR
AI07437
RESET
tNLNH
Warm Reset
tOPR
V
CC
V
CC
(min)
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