參數(shù)資料
型號： uPSD3251
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設(shè)備)
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核（帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設(shè)備）
文件頁數(shù)： 92/128頁
文件大小： 1566K
代理商： UPSD3251
μPSD3251F
92/128
Output Macrocell (OMC)
Eight of the Output Macrocells (OMC) are con-
nected to Ports B pin and are named as McellAB0-
McellAB7. The other eight macrocells are connect-
ed to Ports B and C pins and are named as
McellBC0-McellBC7. If an McellBC output is not
assigned to a specific pin in PSDsoft, the Macro-
cell Allocator block assigns it to either Port B or C.
The Output Macrocell (OMC) architecture is
shown in Figure 46. As shown in the figure, there
are native product terms available from the AND
Array, and borrowed product terms available (if
unused) from other Output Macrocells (OMC). The
polarity of the product term is controlled by the
XOR gate. The Output Macrocell (OMC) can im-
plement either sequential logic, using the flip-flop
element, or combinatorial logic. The multiplexer
selects between the sequential or combinatorial
logic outputs. The multiplexer output can drive a
port pin and has a feedback path to the AND Array
inputs.
The flip-flop in the Output Macrocell (OMC) block
can be configured as a D, T, JK, or SR type in PS-
Dsoft. The flip-flop
’
s clock, preset, and clear inputs
may be driven from a product term of the AND Ar-
ray. Alternatively, CLKIN (PD1) can be used for
the clock input to the flip-flop. The flip-flop is
clocked on the rising edge of CLKIN (PD1). The
preset and clear are active High inputs. Each clear
input can use up to two product terms.
Table 66. Output Macrocell Port and Data Bit Assignments
Note: 1. Port PC0, PC1, PC5 and PC6 are assigned to JTAG pins, and are not available as macrocell outputs
Output
Macrocell
Port
Assignment
(1)
Native Product Terms
Maximum Borrowed
Product Terms
Data Bit for Loading or
Reading
McellAB0
Port B0
3
6
D0
McellAB1
Port B1
3
6
D1
McellAB2
Port B2
3
6
D2
McellAB3
Port B3
3
6
D3
McellAB4
Port B4
3
6
D4
McellAB5
Port B5
3
6
D5
McellAB6
Port B6
3
6
D6
McellAB7
Port B7
3
6
D7
McellBC0
Port B0
(2)
4
5
D0
McellBC1
Port B1
(2)
4
5
D1
McellBC2
Port B2, C2
4
5
D2
McellBC3
Port B3, C3
4
5
D3
McellBC4
Port B4, C4
4
6
D4
McellBC5
Port B5
(2)
4
6
D5
McellBC6
Port B6
(2)
4
6
D6
McellBC7
Port B7, C7
4
6
D7
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