參數(shù)資料
型號： uPSD3251
廠商： 意法半導體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設(shè)備)
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核（帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設(shè)備）
文件頁數(shù)： 120/128頁
文件大小： 1566K
代理商： UPSD3251
μPSD3251F
120/128
Figure 62. Input Macrocell Timing (product term clock)
Table 92. Input Macrocell Timing (5V Device)
Note: 1. Inputs from Port B and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to t
AVLX
and t
LXAX
.
Table 93. Program, WRITE and Erase Times (5V Device)
Symbol
Note: 1. Programmed to all zero before erase.
2. The polling status, DQ7, is valid t
Q7VQV
time units before the data byte, DQ0-DQ7, is valid for reading.
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Unit
t
IS
Input Setup Time
(Note
1)
0
ns
t
IH
Input Hold Time
(Note
1)
15
+ 10
ns
t
INH
NIB Input High Time
(Note
1)
9
ns
t
INL
NIB Input Low Time
(Note
1)
9
ns
t
INO
NIB Input to Combinatorial Delay
(Note
1)
34
+ 2
+ 10
ns
Parameter
Min.
Typ.
Max.
Unit
Flash Program
8.5
s
Flash Bulk Erase
(1)
(pre-programmed)
3
30
s
Flash Bulk Erase (not pre-programmed)
5
s
t
WHQV3
Sector Erase (pre-programmed)
1
30
s
t
WHQV2
Sector Erase (not pre-programmed)
2.2
s
t
WHQV1
Byte Program
14
150
μs
Program / Erase Cycles (per Sector)
100,000
cycles
t
WHWLO
Sector Erase Time-out
100
μs
t
Q7VQV
DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)
(2)
30
ns
t
INH
t
INL
t
INO
t
IH
t
IS
PT CLOCK
INPUT
OUTPUT
AI03101
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