參數(shù)資料
型號： uPSD3251
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設(shè)備)
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核（帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設(shè)備）
文件頁數(shù)： 105/128頁
文件大?。?/td> 1566K
代理商： UPSD3251
105/128
μPSD3251F
Power-down Mode.
By default, if you enable the
APD Unit, Power-down Mode is automatically en-
abled. The device enters Power-down Mode if Ad-
dress Strobe (ALE) remains inactive for fifteen
periods of CLKIN (PD1).
The following should be kept in mind when the
PSD Module is in Power-down Mode:
–
If Address Strobe (ALE) starts pulsing again, the
PSD Module returns to normal Operating mode.
The PSD Module also returns to normal Operat-
ing mode if the RESET input is High.
–
The MCU address/data bus is blocked from all
memory and PLDs.
–
Various signals can be blocked (prior to Power-
down Mode) from entering the PLDs by setting
the appropriate bits in the PMMR registers. The
blocked signals include MCU control signals
and the common CLKIN (PD1).
–
Note:
Blocking CLKIN (PD1) from the PLDs
does not block CLKIN (PD1) from the APD Unit.
–
All memories enter Standby Mode and are
drawing standby current. However, the PLD and
I/O ports blocks do
not
go into Standby Mode
because you don
’
t want to have to wait for the
logic and I/O to
“
wake-up
”
before their outputs
can change. See Table 76 for Power-down
Mode effects on PSD Module ports.
–
Typical standby current is of the order of micro-
amperes. These standby current values as-
sume that there are no transitions on any PLD
input.
Other Power Saving Options.
The PSD Module
offers other reduced power saving options that are
independent of the Power-down Mode. Except for
the SRAM Standby, they are enabled by setting
bits in PMMR0 and PMMR2.
Figure 54. Enable Power-down Flow Chart
Table 76. Power-down Mode
’
s Effect on Ports
Port Function
Pin Level
MCU I/O
No Change
PLD Out
No Change
Address Out
Undefined
Enable APD
Set PMMR0 Bit 1 = 1
PSD Module in Power
Down Mode
ALE idle
for 15 CLKIN
clocks
RESET
Yes
No
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 2 through 6.
AI06609
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