參數(shù)資料
型號： uPSD3251
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設(shè)備)
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核（帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設(shè)備）
文件頁數(shù)： 28/128頁
文件大小： 1566K
代理商： UPSD3251
μPSD3251F
28/128
μPSD3251F HARDWARE DESCRIPTION
The μPSD3251F device has a modular architec-
ture with two main functional modules: the MCU
Module and the PSD Module. The MCU Module
consists of a standard 8032 core, peripherals and
other system supporting functions. The PSD Mod-
ule provides configurable Program and Data mem-
ories to the 8032 CPU core. In addition, it has its
own set of I/O ports and a PLD with 16 macrocells
for general logic implementation. Ports B, C, and
D are general purpose programmable I/O ports
that have a port architecture which is different from
Ports in the MCU Module.
The PSD Module communicates with the CPU
Core through the internal address, data bus (A0-
A15, D0-D7) and control signals (RD_, WR_,
PSEN_ , ALE, RESET_). The user defines the De-
coding PLD in the PSDsoft Development Tool and
can map the resources in the PSD Module to any
program or data address space.
Figure 13. μPSD3251F Device Functional Modules
AI07861
4
Channel
ADC
512Kb
Main Flash
Decode PLD
16Kb
SRAM
CPLD - 16 MACROCELLS
JTAG ISP
Port 1
Port 3
2 UARTs
Interrupt
3 Timer /
Counters
256 Byte SRAM
8032 Core
IPort 3, UART,
PSD Internal Bus
8032 Internal Bus
Port 1, Timers and
2nd UART and ADC
Port 4
Port B, PLD
I/O, and GPIO
Port D
GPIO
Port C,
JTAG, PLD I/O,
and GPIO
VCC, GND,
XTAL
128Kb
Secondary
Flash
Dedicated
Pins
I2C
Reset Logic
LVD & WDT
Bus
Interface
Reset
D0-D7
A0-A15
RD,PSEN
WR,ALE
Page Register
PSD MODULE
MCU MODULE
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