參數(shù)資料
型號(hào)： UJA1061
廠商： NXP Semiconductors N.V.
英文描述： Low speed CAN/LIN system basis chip
中文描述： 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片
文件頁(yè)數(shù)： 9/81頁(yè)
文件大?。?/td> 323K
代理商： UJA1061
2004 Mar 22
9
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
An external reset event is applied to the reset input of
the UJA1061. Here, if pin RSTN was already HIGH
before the event (as in Normal, Standby or Flash mode),
any other operating mode of the UJA1061 is left
immediately and the external reset pulse is lengthened
by the UJA1061 to the user-defined reset period.
An external reset event does not allow the UJA1061 to
be forced back to Start-up mode out of Restart or
Fail-safe mode to deal with a chattering and/or a
clamped reset line. In such a case, the system has to
end within Fail-safe mode with the lowest possible
power consumption.
An undervoltage is detected at the V1 supply. In this
case any other operating mode of the UJA1061 in which
V1 was active (Normal, Start-up or Flash mode) is left
immediately and the external reset pulse is lengthened
by the UJA1061 to the user-defined reset period.
Further undervoltage conditions do not allow the
UJA1061 to be forced out of Restart or Fail-safe mode
in order to deal with continuous undervoltages on V1.
The system has left the fail-safe condition due to a
wake-up event with a running oscillator. Here again the
long reset period is applied in order to guarantee a
proper system start.
When the reset period is finished (pin RSTN is released
and goes HIGH) the watchdog waits for initialization. If the
watchdog initialization is correct, the selected operating
mode is entered. The only correct watchdog initialization
out of start-up is a successful SPI access of the mode
register, whereby the init Normal mode or init Flash mode
is selected.
As Start-up mode is the ‘home page’ of the UJA1061,
below a mode-oriented overview of the events, which
result in a mode transition towards Start-up mode.
Being in Sleep mode, Start-up mode will be entered using
the user-defined reset pulse if:
Activity on the CAN-bus or LIN-bus is detected
A falling edge on the local input port is detected
A watchdog time-out occurs (used for cyclic wake-up of
the module)
A failure at the V3 power supply pin occurs (only if V3 is
active).
Being in Fail-safe mode, Start-up mode will be entered
using the long reset pulse if:
Activity ontheCAN-busor theLIN-busand theoscillator
functions correctly again
A falling edge on the local input port is detected and the
oscillator functions correctly again.
Being in Normal, Standby or Flash mode, Start-up mode
will be entered if:
A falling edge on pin RSTN is detected. If pin RSTN is
held LOW externally for a long period, Fail-safe mode
will be entered directly since a serious ECU problem
exists
An unwanted undervoltage condition at V1. In the case
where V1 is active and then falls below the undervoltage
detection threshold the UJA1061 immediately enters
Start-up mode forcing pin RSTN LOW. If V1 keeps
within the undervoltage condition for a long time, this
againisanindicationofamalfunctioningapplicationand
theUJA1061entersFail-safemodewithoutfirstentering
Restart mode. A reset as a result of this condition can
occur only when V1 was already active with a HIGH
level on pin RSTN
Start-up mode also will be entered out of Standby mode on
the following events (restarting a continuously powered
microcontroller with a user-defined reset pulse):
A wrong mode register code access occurs
The microcontroller supply current increases as a result
of an externally activated microcontroller in the
Watchdog OFF mode if the reset option is selected
A watchdog time-out did occur if the reset option is
selected
Activity on the CAN-bus or LIN-bus is detected if the
reset option is selected, even if the microcontroller did
request a change to Sleep mode during a pending
wake-up
A falling edge on the local input port is detected if the
reset option is selected, even if the microcontroller did
request a change to Sleep mode during a pending
wake-up
After an ignored interrupt. Depending on the application
software, certain events can force an interrupt or a reset
event. In the case of interrupts, these interrupt events
have to be served by the application software within
256 ms. If the software does not react within this time,
the UJA1061 will force a transition into Start-up mode
with a defined reset behaviour.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UJA1061_10 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW/3V0,512 制造商:NXP Semiconductors 功能描述:
UJA1061TW/3V0512 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP
UJA1061TW/3V3/C/T, 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube
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