參數(shù)資料
型號(hào)： UJA1061
廠商： NXP Semiconductors N.V.
英文描述： Low speed CAN/LIN system basis chip
中文描述： 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片
文件頁(yè)數(shù)： 33/81頁(yè)
文件大?。?/td> 323K
代理商： UJA1061
2004 Mar 22
33
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
6.14.2
M
ODE REGISTER
The mode register has cyclic access during system
operation. Here the watchdog is defined and re-triggered
as well as the current mode of operation is selected.
Furthermore the global enable output (bit EN) as well as
the Software Development Mode (bit SDM) control bit are
defined here. Depending on the system requirements, the
CAN physical medium can be activated with any access to
the CAN Mode bit (CM).
Thisregisterhastobewrittenduringsystemstart-upwithin
256 ms after RSTN has become released (HIGH-level on
RSTN). Any write access is checked for proper watchdog
andsystemmodecoding.Ifanillegalcodeisdetected,this
access is ignored by the UJA1061 and a system reset is
forced according to the state diagram of the system
controller.
Table 3
MOD - Mode register (address 00) bit description
BIT
SYMBOL
DESCRIPTION
VALUE
FUNCTION
15, 14
13
A1, A0
RRS
register address
Read Register Select
00
1
0
1
0
select Mode register
read System Diagnosis register (DIAG)
read System Status register (STAT)
read selected register without writing to Mode register
read selected register and write to Mode register
Normal
operating
mode (ms)
4
20
8
40
16
80
32
160
40
320
48
640
56
1024
64
2048
72
4096
80
OFF
(1)
Normal operating mode
Standby mode
Sleep mode
initializing Normal mode
Flash Programming mode; note 2
initializing Flash mode 1; note 3
no watchdog reset; no interrupt monitoring; no reset
monitoring; no transitions to Fail-safe mode; Fail-safe is
entered only with a V1-undervoltage condition longer than
256 ms
Normal watchdog, interrupt, reset monitoring and fail-safe
behaviour
12
RO
Read Only
11 to 6
NWP[5:0] Nominal Watchdog
Period
Standby
mode (ms)
Flash
Programming
mode (ms)
20
40
80
160
320
640
1024
2048
4096
8192
Sleep mode
(ms)
001001
001100
010010
010100
011011
100100
101101
110011
110101
110110
001
010
100
101
111
011
1
160
320
640
1024
2048
3072
4096
6144
8192
OFF
(1)
5 to 3
OM[2:0]
Operating Mode
2
SDM
Software
Development Mode
(4)
0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UJA1061_10 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW/3V0,512 制造商:NXP Semiconductors 功能描述:
UJA1061TW/3V0512 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP
UJA1061TW/3V3/C/T, 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類(lèi)型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube
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