參數(shù)資料
型號(hào): UJA1061
廠商: NXP Semiconductors N.V.
英文描述: Low speed CAN/LIN system basis chip
中文描述: 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片
文件頁(yè)數(shù): 36/81頁(yè)
文件大小: 323K
代理商: UJA1061
2004 Mar 22
36
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
Note
1.
The Reset Source register is updated with each reset event and not cleared. The last reset event is captured.
4
EWS
Edge Wake Status
1
pin WAKE negative edge event detected; cleared upon
read
pin WAKE no edge detected
chip temperature exceeds the warning limit
chip temperature is below the warning limit
no watchdog reset; no interrupt monitoring; no reset
monitoring; no transitions to Fail-safe mode; only during a
V1 undervoltage longer than 256 ms
normal watchdog interrupt, reset monitoring and fail-safe
behaviour
pin EN output activated, a (V1-related) HIGH level is driven
pin EN output released a LOW level is driven
Power-on reset; first connection of BAT42
or
BAT42 below
power-on voltage threshold; cleared after a
successfully-entered Normal operating mode or Flash
Programming mode
No Power-on reset
0
1
0
1
3
TWS
TemperatureWarning
Status
2
SDMS
Software
Development Mode
Status
0
1
EN
Enable status
1
0
1
0
PWONS
Power-on reset
Status
0
BIT
SYMBOL
DESCRIPTION
VALUE
FUNCTION
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