參數(shù)資料
型號： UJA1061
廠商： NXP Semiconductors N.V.
英文描述： Low speed CAN/LIN system basis chip
中文描述： 低高速CAN / LIN系統(tǒng)基礎芯片
文件頁數(shù)： 70/81頁
文件大?。?/td> 323K
代理商： UJA1061
2004 Mar 22
70
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
t
BUS(fail)(recover)
bus failure recovery time
bus failure HxBAT
bus failure HxVCC
bus failures LxGND and HxL; Active
mode, On-line and Selective Sleep
mode; V
V2
= 5 V
bus failures LxGND and HxL
bus failure LxBAT; Active mode,
On-line and Selective Sleep mode;
V
V2
= 5 V
continuously dominant clamped
CAN-bus Active mode, On-line and
Selective Sleep mode; V
V2
= 5 V
Active mode, On-line and Selective
Sleep mode; V
V2
= 5 V;
TXDC = logic 0 V
Off-line
125
0.3
7
750
1.6
38
μ
s
ms
μ
s
0.9
125
1.6
750
ms
μ
s
1
5
μ
s
t
TXDC(dom)
TXDC permanent
dominant disable time
1.5
6
ms
t
CANH(d1)
,
t
CANL(d1)
minimum dominant time
first pulse for wake-up on
pins CANH, CANL
minimum recessive time
pulse (after first
dominant) for wake-up on
pins CANH, CANL
minimum dominant time
second pulse for wake-up
on pins CANH, CANL
CANL dominant time
entering Normal mode
and TXDC goes
dominant
required recessive or
dominant time for
entering Off-line
7
38
μ
s
t
CANH(rec)
,
t
CANL(rec)
Off-line
3
10
μ
s
t
CANH(d2)
,
t
CANL(d2)
Off-line
0
3
μ
s
t
CANL(dom)
V
CANL
> 8 V, first dominant bit after
entering Active mode
3
10
μ
s
t
offline
On-line or Selective Sleep mode;
COTC = logic 0; CM = logic 0
On-line or Selective Sleep mode;
COTC = logic 1; CM = logic 0
On-line; CM = logic 0; coming out of
Off-line
Active mode, On-line and Selective
Sleep mode; V
V2
= 5 V; TXDC
recessive
bus failures H//, L//, HxGND and
LxVCC; Active mode, On-line and
Selective Sleep mode; V
V2
= 5 V
bus failures H//, L//, HxGND and
LxVCC; Active mode, On-line and
Selective Sleep mode; V
V2
= 5 V
50
66
ms
200
265
ms
400
530
ms
t
CANH,
t
CANL
ground shift sampling
time required for CANH,
CANL voltage level
pulse count difference
between CANH and
CANL for failure detection
dominant pulse count on
CANH and CANL for
failure recovery
20
80
μ
s
t
PC
4
pulses
4
pulses
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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相關代理商/技術參數(shù)
參數(shù)描述
UJA1061_10 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW/3V0,512 制造商:NXP Semiconductors 功能描述:
UJA1061TW/3V0512 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP
UJA1061TW/3V3/C/T, 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube
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