參數(shù)資料
型號(hào)： UJA1061
廠商： NXP Semiconductors N.V.
英文描述： Low speed CAN/LIN system basis chip
中文描述： 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片
文件頁(yè)數(shù)： 44/81頁(yè)
文件大?。?/td> 323K
代理商： UJA1061
2004 Mar 22
44
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
6.14.8
S
YSTEM CONFIGURATION REGISTER
This register, only accessible in Normal and Standby modes, allows the UJA1061 behaviour to be configured.
Table 9
SC - System Configuration register (address 10) bit description
Note
1.
For fail-safe reasons, this bit is set automatically when entering the Reset state.
BIT
15, 14
13
SYMBOL
A1, A0
RRS
DESCRIPTION
register address
Read Register Select
VALUE
10
1
0
1
FUNCTION
select System Configuration register
read the General Purpose Feedback register (GPF0)
read the System Configuration Feedback register (SCF)
read register selected by RRS without writing to System
Configuration register
read register selected by RRS and write to System
Configuration register
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
1.5 V; exceeding this level forces an interrupt
0.75 V; exceeding this level forces an interrupt
20 ms system reset is selected; default after power-up
1 ms system reset is selected
Cyclic mode 2; 350
μ
s ON/32 ms period
Cyclic mode 1; 350
μ
s ON/16 ms period
continuously ON
OFF; also reset to 00 in Fail-safe mode, or after a negative
edge has been detected at the external RSTN pin, or a
short-circuit situation is detected at V3
the reduced V1 undervoltage threshold is selected
the normal V1 undervoltage threshold is selected
an increasing V1 current causes a reset event if the
watchdog was disabled during Standby mode
an increasing V1 current just activates the watchdog again
during Standby mode
wake-up functionality at WAKE pin enabled
wake-up functionality at WAKE pin disabled
WAKE mode cyclic sample
WAKE mode continuous sample
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
INH/LIMP home pin HIGH
INH/LIMP home pin floating
12
RO
Read Only
0
11
reserved
0
10
reserved
0
9
GSTHC
GND Shift Threshold
Control
1
0
8
RLC
Reset Length Control
1
(1)
0
11
10
01
00
7, 6
V3C
V3 Control
5
V1RTHC
V1 Reset Threshold
Control
1
0
1
4
V1CMC
V1 Current Monitor
Control
0
3
WEN
WAKE Enable
1
0
1
0
0
2
WSC
WAKE Sample
Control
1
reserved
0
IC
INH control
1
0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UJA1061_10 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW/3V0,512 制造商:NXP Semiconductors 功能描述:
UJA1061TW/3V0512 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP
UJA1061TW/3V3/C/T, 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube
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