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參數(shù)資料
| 型號： | UJA1061 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low speed CAN/LIN system basis chip |
| 中文描述： | 低高速CAN / LIN系統(tǒng)基礎芯片 |
| 文件頁數(shù)： | 25/81頁 |
| 文件大小： | 323K |
| 代理商： | UJA1061 |
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2004 Mar 22
25
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
Table 1
CAN-bus, RXD and TXD failure detection
Note
1.
CANL stays active with weak short-circuits to BAT due to wake-up requirements within large networks.
FAILURE
DESCRIPTION
DRIVER AND BIASING CIRCUIT DISABLING
HxVCC
HxBAT
HxGND
LxBAT
LxGND
LxVCC
HxL
H//
L//
Bus Dom
CANH to V
CC
(5 V) short-circuit
CANH to BAT (14 and 42 V) short-circuit
CANH to GND short-circuit
CANL to BAT (14 and 42 V) short-circuit
CANL to GND short-circuit
CANL to V
CC
(5 V) short-circuit
CANH to CANL short-circuit
CANH interrupted
CANL interrupted
bus is continuously clamped dominant (double
failure); even within Single-wire mode the receiver
remains dominant
bus is continuously clamped recessive (double
failure); driving messages to the bus is not
possible even while the driver is active
pin TXDC is continuously clamped dominant
(handles also RXDC to TXDC short-circuits)
pin RXDC is continuously clamped recessive
pin RXDC is continuously clamped dominant
CANH off, weak RTH
CANH off, weak RTH
none
CANL off, weak RTL; note 1
CANL off, weak RTL
none
CANL off, weak RTL
none
none
CANL off, weak RTL
Bus Rec
none
TxDC Dom
transmitter disabled but no change in biasing
RxDC Rec
RxDC Dom
transmitter disabled but no change in biasing
none
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相關(guān)代理商/技術(shù)參數(shù) |
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