參數(shù)資料
型號: UJA1061
廠商: NXP Semiconductors N.V.
英文描述: Low speed CAN/LIN system basis chip
中文描述: 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片
文件頁數(shù): 38/81頁
文件大?。?/td> 323K
代理商: UJA1061
2004 Mar 22
38
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
Note
1.
V2D becomes cleared upon a short-circuit situation on V2 (overload) while V2 is active. In parallel, V2 becomes
disabled in order to protect the system from high current consumption. V2 will be restarted setting V2D with the
following events:
a) By setting CAN mode
b) During a HIGH-to-LOW transition of the CTC bit (Physical Layer Control register) activating the CAN-transmitter
c) During a transition from Off-line into On-line
d) During a transition from Off-line into Selective Sleep mode.
1, 0
CANMD
CAN mode diagnosis
11
10
01
00
CAN is within Active mode
CAN is within On-line mode
CAN is within Selective Sleep mode
CAN is within Off-line mode
BIT
SYMBOL
DESCRIPTION
VALUE
FUNCTION
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