參數(shù)資料
型號： UJA1061
廠商： NXP Semiconductors N.V.
英文描述： Low speed CAN/LIN system basis chip
中文描述： 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片
文件頁數(shù)： 72/81頁
文件大?。?/td> 323K
代理商： UJA1061
2004 Mar 22
72
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
Battery monitoring
t
BAT42(L)
BAT42 LOW time for
setting Power-on reset
flag
BAT42 LOW time for
setting BAT fail flag
5
20
μ
s
t
SENSE(L)
5
20
μ
s
Power supply V1 (pin V1)
t
V1(CLT)
V1 clamped LOW time
during ramp-up of V1
LOW or HIGH time to
change from V1 = 3 V to
V1 = 5 V and back
Start-up mode; V1 active
229
283
ms
t
V1MODE
V1 active
5
20
μ
s
Power supply V2 (pin V2)
t
2(CLT)
V2 clamped LOW time
during ramp-up V2
V2 active
28
36
ms
Power supply V3 (pin V3)
t
W(CS)
cyclic sense period
V3C = 10; see Fig.12
V3C = 11; see Fig.12
V3C = 10; see Fig.12
V3C = 11; see Fig.12
180
360
14
28
220
440
18
36
μ
s
μ
s
ms
ms
t
on(CS)
cyclic sense on-time
Wake-up input (pin WAKE)
t
WU
input port filter time
V
BAT42
= 5 to 27 V
V
BAT42
= 27 to 52 V
V3C = 11 or 10; see Fig.12
10
50
310
120
250
390
μ
s
μ
s
μ
s
t
su(CS)
cyclic sense sample
set-up time
Watchdog
t
WD(ETP)
earliest trigger point
programmed Nominal Watchdog
Period (NWP); Normal mode
programmed Nominal Watchdog
Period (NWP); Normal mode,
Standby and Sleep mode
watchdog time-out in Start-up mode
0.45
×
NWP
0.9
×
NWP
0.55
×
NWP
1.1
×
NWP
t
WD(LTP)
latest trigger point
t
WD(init)
Reset output (pin RSTN)
watchdog init period
229
283
ms
t
RSTN(ext)
external reset monitoring
time
clamped HIGH time,
pin RSTN
interrupt monitoring time
reset lengthening time
229
283
ms
t
RSTN(CHT)
RSTN driven LOW internally but
RSTN pin remains HIGH
INTN = logic 0
after internal or external reset has
been released; RST = logic 0
after internal or external reset has
been released; RST = logic 1
115
141
ms
t
RSTN(INT)
t
RSTNL
229
0.9
283
1.1
ms
ms
18
22
ms
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UJA1061_10 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW/3V0,512 制造商:NXP Semiconductors 功能描述:
UJA1061TW/3V0512 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP
UJA1061TW/3V3/C/T, 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube
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